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What does CSP stand for?
CSP stands for chip scale package or chip size package. It is a chip housing that is slightly larger than the chip itself.
total search3668 articles
2007-07-10 Understanding flip-chip and chip-scale package technologies and their applications
This article first defines the terms "flip chip" and "chip-scale package" and explains the technical development of wafer-level packaging (WLP) technology.
2000-07-01 Trends in multi-chip package integration
Wafer level packaging (WLP) technologies have recently attracted much development activity, innovation and investment. Here are some of the opportunities and obstacles for WLP and multi-chip package integration approaches.
2004-01-28 Toshiba package achieve thinner chips
With a 1.4mm height, the Multi Chip Package (MCP) from Toshiba Corp. stacks a total of nine layers of components.
2002-05-02 Toshiba chip package is 30 percent smaller
Toshiba Corp. has announced that it has developed a stacked multi-chip package (MCP) that measures 7-by-10mm30 percent smaller than the company's current MCPs that measure 9-by-12mm.
2010-07-09 TI turns to pillar flip-chip for 45-/40nm node
Texas Instruments Inc. is embracing an emerging technology called fine-pitch copper pillar flip-chip packages for devices at the 45-/40nm node and below
2009-05-11 TI intros PicoStar package
Portable consumer electronics designers can save board space with ICs housed in TI's new PicoStar package, which is about as thin as a human hair
2005-03-25 Tessera signs up Fujitsu as chip packaging licensee
Tessera Technologies Inc. has signed a technology licensing agreement with Fujitsu Ltd for packaging intellectual property.
2002-09-26 STMicro memory package reduces size by 23 percent
STMicroelectronics has introduced the MSOP8 package for use in their serial nonvolatile memory product that provides about 23 percent reduction in size, compared to the TSSOP8 package
2005-01-18 Samsung to supply multi-chip packages to Sony PSP
Samsung Electronics Co. Ltd will supply multi-functional multi-chip package (MCP) solutions for Sony Corp.'s PlayStation portable (PSP) game system and to manufacturers of digital cameras.
2006-11-03 Samsung announces 16-chip MCP technology
Samsung Electronics announced that it has developed the industry's 'first' process to enable the manufacture of a 16-chip multi-chip package of memory.
2008-10-01 Reap the rewards of package-aware design
Chip designers must consider package routability, power delivery and I/O behavior during the initial I/O planning process. To do so, they should combine package-aware I/O planning with automated floor-plan synthesis, which can be very cost-effective for the chip floor plan and the package layout.
2005-05-17 Philips Semiconductor CTO outlines system-in-package challenges
The next step forward in integration has to address system-in-package (SIP) issues and needs EDA tools with broader scope and greater standardization of approach, according to Rene Penning de Vries, chief technology officer of Philips Semiconductors
2002-04-17 Philips IC package is 75 percent smaller
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2004-05-06 NxGen to make microZ package from Tessera
Tessera Technologies Inc. and NxGen Electronics Inc. have signed a new licensing agreement.
2006-01-12 New wafer-level package tech from National
National Semiconductor announced the micro SMDxt chip package, the company's newest generation of wafer-level package technologies.
2012-09-10 MediaTek's reference chip to boost eMCP shipments
DRAMeXchange said the company's duo core MT6577 chipsets are being incorporated with eMMC + Multi Chip Package function as a part of its standard memory chip design.
2010-06-04 IPAD 500?m Flip Chip: package description and recommendations for use
This application note provides package and usage recommendation information for 500?m pitch Flip Chips
2015-03-09 IoT drives chip packaging innovation
The need for high performance multi-functional devices in a single package is pushing the industry to innovate in multi-chip packaging. This high level of integration has presented huge challenge.
2005-12-20 Inphi tapes out high-speed chip with Cadence platform
Cadence announced that Inphi has successfully taped out a complex high-speed chip using the Cadence Encounter digital IC design platform
2013-01-31 Infineon unveils 'Coil on Module' chip package
Geared for dual Interface bank and credit cards, the package combines a security chip and antenna that makes an RF connection to the antenna embedded on the plastic payment card.
2014-08-22 Infineon buys IR to reposition itself in chip industry
The German company is paying $3 billion in cash for Internal Rectifier, an acquisition that will expand its expertise in compound semiconductors, as well as facilitate a stronger market presence.
2003-03-28 IC, package co-design proving elusive, techies say
IC package design has become a huge bottleneck for getting chips out the door, but there are few automated tools that can help, according to panelists at the International Symposium on the Quality of Electronic Design
2006-12-11 Hynix unveils 512Mbit mobile DRAM chip
Hynix Semiconductor Inc. has developed a 512-Mbit mobile DRAM that meets industry chip standards and operates at 200MHz
2009-06-16 Flip-Chip 300?m recommendations for audio power amplifier
This application note describes the Flip-Chip CSP features and species how ST's customers can use them
2007-10-25 EDA's big three unready for 3D chip packaging
Without design tools to allow exploration and tradeoffs to be made in 3D layouts, engineers are restricted to design in two dimensions and occasionally stack chips crudely. But without a clear market for 3D design EDA vendors are unlikely to offer tools.
2001-06-15 CR-15 package handling and mounting procedure
This application note suggests some recommendations for proper handling and mounting of the CR-15 low-thermal resistance package
2011-03-28 Chip supply disruption temporary, says analyst
Analysts expect the earthquake's impact on the chip supply chain to be temporary and limited, basing their prediction on events following the 7.6-magnitude Taiwan earthquake in 1999
2003-09-05 Chip package venture established in Jiangyin
Jiangsu Changjiang Electronics Technology Co. Ltd has set up a joint venture, named Jiangyin Changjiang Electronics, with Singapore-based APS Inc. in Jiangyin.
2008-10-01 Chip package options abound
When creating a new IC, device packaging is often overlooked until the end of process. However, choosing the right package can reduce time-to-market and create tangible benefits for customers. Here is a look at some of the available options and what they have to offer
2008-08-27 Cadence tool steps up IC package, SiP designs
The release of SPB 16.2, due in November of this year, from Cadence Design Systems, delivers advanced IC package/system-in-package miniaturization, design cycle reduction and DFM-driven design, along with a new power integrity modeling solution
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