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2006-07-06 X-ray analyzer eases advanced chip packaging
Xradia said the MicroXCT is suited for the engineering and failure analysis of next-generation semiconductor packages, including multistacked die and flip-chip architectures
2005-08-16 Water-filled wafers streamline chip cooling
Researchers develop a chip-cooling process that hopes to replace bulky, bolt-on metal towers used in microprocessors
2009-06-29 Ultrathin chip shielding provides flexibility
Autosplice Inc. has announced ChipShields, which provide shielding during the manufacturing of the chip packages. The shields are manufactured to ultrathin dimensions
2004-07-14 Two firms apply carbon nanotubes to chip packaging
Carbon Nanotechnologies Inc. (CNI) has agreed with Kostat Inc. to develop and commercialize conductive polymers for module trays, carrier tapes and other semiconductor packaging and chip and die delivery applications.
2003-07-07 TSMC, Amkor partner on flip-chip packaging
Amkor Technology has developed and qualified wirebond and flip-chip packaging for devices manufactured on TSMC's advanced low-k process technologies.
2011-04-11 TSMC enters chip-packaging arena
TSMC will soon open a bumping facility and offer silicon interposers and TSV technologies for 3D chips, but will remain focused on the foundry market and will not compete against subcontractors.
2008-08-11 Trio seeks to cut costs in chip packaging
Infineon has granted licenses for its embedded Wafer-Level BGA chip packaging technology to competitor STMicroelectronics as well as STATS ChipPAC to lower costs and achieve higher market acceptance.
2010-07-09 TI turns to pillar flip-chip for 45-/40nm node
Texas Instruments Inc. is embracing an emerging technology called fine-pitch copper pillar flip-chip packages for devices at the 45-/40nm node and below
2005-03-25 Tessera signs up Fujitsu as chip packaging licensee
Tessera Technologies Inc. has signed a technology licensing agreement with Fujitsu Ltd for packaging intellectual property
2010-12-15 STATS ChipPac flip chip biz grows over 50
Semicon test and packaging provider STATS ChipPAC announced its flip chip business grew more than 50 percent in 2010. The company shipped more than 250 million flip chip packaging units.
2005-09-02 Singapore packager to expand flip-chip capacity
Assembly and test company STATS ChipPAC Ltd is expanding its capacity for flip-chip assembly
2007-01-16 QFN packaging guidelines for RF designers
It seems such an irrelevant detail, but the component package is a strong determinant factor over layout flexibility.
2005-08-11 Politicians hurting Taiwan's chip efforts in China
Taiwan's government is not likely to relax semiconductor industry investments or export control policies in China in the near term, because of political confusion on the island, according to the U.S.-Taiwan Business Council.
2006-01-30 Pillars replace balls in Intel processor packaging
Intel's Presler and Yonah processors make use of copper pillar bumping as an alternative to lead-tin solder balls, according to Chipworks.
2007-04-23 PIDA: Taiwan dominates blue LED chip capacity segment
Taiwan emerges as the top region in blue LED chip capacity and occupied the second spot in LED chip packaging in 2006, according to Taiwan's Photonics Industry Technology & Development Association.
2005-10-21 Packaging conference to explore 3D, SIP
Building on the first International Wafer-Level Packaging Congress (IWLPC) event, the second IWLPC conference will explore three-dimensional (3D) chip-packaging and other technologies.
2004-08-31 LSI Logic offers lead-free chip products
In preparing for a global initiative to rid lead and other hazardous materials from electronic products, LSI Logic is meeting customer demands by offering chip products with lead-free packaging.
2002-10-24 LSI Logic extends reach of wirebond packaging
LSI Logic Corp. has developed a form of wirebond packaging that places bonding pads directly on top of a chip's active I/O circuitry.
2015-03-09 IoT drives chip packaging innovation
The need for high performance multi-functional devices in a single package is pushing the industry to innovate in multi-chip packaging. This high level of integration has presented huge challenge.
2007-10-18 Industrial affiliation program tackles 32nm IC packaging
Two research centers are inviting industry partners to participate in an advanced research program on next-generation flip-chip and substrate technologies
2005-09-29 IDT's flip-chip packaged monolithic NSEs now RoHS-compliant
IDT disclosed that it has begun volume production of its RoHS-compliant flip-chip packaged monolithic 512Kx36 (18Mb) and 256Kx36 (9Mb) network search engines with dual Network Processor Forum Look Aside interfaces
2005-09-21 IDT offers network engines in RoHS-compliant flip-chip packaging
Integrated Device Technology Inc. (IDT) has begun volume production of its RoHS (Restriction on Hazardous Substances)-compliant flip-chip packaged monolithic 512Kx36 (18Mbit) and 256Kx36 (9Mbit) network search engines (NSEs) with dual Network Processor Forum (NPF) Look Aside (LA-1) interfaces
2009-10-23 IC packaging becomes more challenging
Analog design remains challenging but IC packaging is becoming an issue in the arena
2012-01-19 IC market to tug chip packaging, testing sales
For Q1, testing and packaging firms forecast a dip in sales from 5-10 percent, although a rebound is forecast for Q3
2004-05-21 IBM jettisons IC-packaging units, sells plants to Amkor
IBM Corp. has moved to jettison its chip assembly and packaging operations, announcing a major deal with Amkor Technology Inc.
2004-04-14 HKSTP, ASAT to promote chip packaging in HK, China
The Hong Kong Science and Technology Parks Corp. (HKSTP) has formed a strategic alliance with ASAT Holdings Ltd, a provider of semiconductor package design, assembly, and test services, to cooperatively promote IC packaging and test related services in Hong Kong and mainland China
2006-08-03 Freescale cuts die area, thickness with new chip packaging tech
Freescale's proprietary redistributed chip packaging technique delivers about a 30 percent reduction in packaged-die area and thickness.
2011-03-10 Flip chip packaging boasts 40% lower cost
STATS ChipPAC releases a flip chip packaging technology, fcCUBE, that boasts high input/output density, high performance and reliability in advanced silicon nodes.
2001-08-01 Few-chip packaging: An MCM renaissance
Kevin Rinebold explains how FCP is a more attractive risk management strategy than SoC for combining IP from multiple sources or mixed semiconductor technology.
2007-10-25 EDA's big three unready for 3D chip packaging
Without design tools to allow exploration and tradeoffs to be made in 3D layouts, engineers are restricted to design in two dimensions and occasionally stack chips crudely. But without a clear market for 3D design EDA vendors are unlikely to offer tools.
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