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2014-12-09 Reduce power SoC consumption in the interconnect
Here's a modular approach to SoC interconnect for reducing power consumption. The modular concept is different because it consists of a distributed architecture of various components.
2007-03-16 New tools solve CDC-analysis troubles
CDCs have become a leading cause of design errors. Errors may even find their way into silicon, necessitating respins.
2014-03-04 Analyse CDC violations in million-gate SoC (Part 1)
Learn how to constrain the design to avoid unwanted violations and analyse the remaining CDC paths flagged by tool.
2004-06-08 Atrenta releases RTL checker
Atrenta's assertion-based functional analysis tool checks whether user RTL is functionally correct and fixes problems to minimize iterations between simulation and synthesis.
2004-05-18 0-In tool verifies metastability effects
Claiming a "breakthrough" solution for the automatic verification of metastability effects, 0-In Design Automation is preparing Archer CDC-FX, an addition to its clock-domain crossing (CDC) verification tool
2003-08-07 RTL tool provider snags $5.3M funding
Atrenta Inc., provider of RTL "predictive analysis" solutions, has secured $5.3M in series B venture capital funding.
2013-12-03 RTL signoff: A design imperative
"RTL Signoff" as an established concept has gained significance in the last year. However, writes Atrenta's Piyush Sancheti, does a commonly accepted definition of RTL signoff exist?
2004-11-18 Cadence Encounter Conformal 5.0 with enhanced verification capability
Cadence Design Systems announced enhancements to its Encounter Conformal technology.
2014-01-21 Advantages of hierarchical flow for SoC design
Learn why it is critical to minimize lengthy problem detection and fix issues as early as possible using a comprehensive hierarchical SoC methodology.
2003-01-31 0-In pumps up assertion-based verification suite
Armed with two new products and new technology, 0-In Design Automation is rolling out version 2.0 of its assertion-based verification suite.
2012-08-08 Grasping power awareness in RTL design analysis
Find out how formats such as CPF and UPF play a key role in capturing power intent for RTL design analysis and verification.
2011-10-12 A practical way of inspecting IP quality
Find out how to set up a process which can give you solid incoming IP quality inspectiona process that quite likely finds potential problems you may not have checked before, all with a minimum of overhead both in maintenance and in cycle time.
2005-06-01 Driving 10Gb Serial ATCA backplanes
The Backplane Ethernet Task Force is focused on developing three new PHYs: 1000BASE-KX, 10GBASE-KX4 and 10GBASE-KR
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