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2007-03-28 Tool taps clock gating for IC power optimization
Claiming breakthrough technology in IC power optimization, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code.
2006-11-20 Sequence revs clock power with PowerTheater 65
Sequence Design has announced its flagship product for RTL power estimation and managementPowerTheater 65which includes enhanced clock power estimation and reduction as well as improvements to stimulus generation and performance
2013-05-23 Performing synthesis-aware clock analysis
Read about a tool that performs clock structure analysis by tracing complex clock nets and visually presenting them to designers
2007-03-05 Magma tools cut clock tree power draw by 25
Magma Design Automation has introduced a pair of low-power IC implementation and analysis tools that the company claims have been shown to reduce power consumption in nanometer ICs by 25 percent.
2010-05-06 FPGA design suite includes intelligent clock gating
Xilinx has launched a new version of its ISE Design Suite to support its Virtex-6 and Spartan-6 FPGA that include intelligent clock gating technology and timing-driven design preservation.
2006-11-08 Equivalence checker eyes clock gating
The sequential equivalence checker that Calypto Design Systems will release soon promises to automate the verification of clock-gating circuitry.
2006-07-12 Clock implementation tool supports 65nm design flows
Azuro said version 3 of the PowerCentric clock implementation solution provides 15 percent to 25 percent power reduction to support advanced variability-aware design flows at 65nm and below
2011-07-14 Cadence buys clock optimization tech company
Cadence hopes to address SoC performance, power and area challenges with the acquisition of Azuro and its clock optimizing technology
2002-05-01 ARM cranks up the clock of next-generation processor core
ARM Holding Ltd. will make a big performance push with its next-generation ARM11 microarchitecture, which will reach speeds of 750MHz based on 0.13? design rules, according to a presentation posted on the company's Web site.
2013-03-25 Analyse RTL clock gating to cut processor power
The focus on clock gating and the fast turnaround of RTL analysis allow measurable power reductions for typical applications of X86 AMD core.
2009-02-20 Supervisor circuits pack battery backup, CE gating
Maxim Integrated Products has developed the MAX16016/20/21/23/24 low-power, microprocessor supervisory circuits featuring precision power-supply monitoring and battery-control functions.
2006-08-16 Tailor configurable processors for audio codecs
The combination of experimental results coupled with the Xtensa LX configurable processor features and the rapid turnaround possible with the Xtensa Processor Generator have produced an application-tailored processor core capable of delivering excellent performance on a wide range of audio codecs.
2014-01-05 SoC implementation with dependable 50% duty cycles
Here's a new approach to implementing clock dividers in a system-on-chip design that supports both high performance and low power
2015-03-30 Significance of RTL architecture to power analysis
Learn about the advantages of a well defined RTL architecture for power estimation and analysis through a case study of a FIFO design.
2014-11-18 Reducing SoC power: Where should the focus be?
Typically, efforts to manage power consumption in SoC design are focused on the CPU and GPU. The SoC interconnect is one area that needs to be re-evaluated.
2014-12-09 Reduce power SoC consumption in the interconnect
Here's a modular approach to SoC interconnect for reducing power consumption. The modular concept is different because it consists of a distributed architecture of various components.
2003-09-01 Predictive analysis for low-power IA designs
Predictive analysis techniques incorporates low-power design techniques and ensures adherence to new design methodologies.
2006-07-07 Power reduction tool from Azuro extends to 65nm
Azuro has released version 3 of its PowerCentric low power clock implementation tool, which extends the company's power reduction capabilities to support advanced variability-aware design flows at 65nm and below
2015-01-28 Performing automatic ASIC-to-FPGA conversion
Performing ASIC-to-FPGA clock tree conversions by hand is hard and time-consuming for designers, but the use of automated gated clock conversion makes this task much less challenging
2010-10-14 GN ReSound adopts Magma Talus for hearing solutions
According to Magma Design Automation, hearing instrument solution maker GN ReSound has selected the Talus implementation system for its next-generation ICs.
2014-12-19 Examining structural faults that lead to glitches
Learn about the structural faults that can lead to glitches in clocks. We will also tackle some bad design practices that lead to glitches in data.
2014-11-06 Enhance SoC efficiency with multi-bit flip-flops
Here's a look at the architecture of multi-bit flip-flops, its merits and drawbacks. It also tackles the results of its implementation in a particular design and the various areas of concern.
2006-10-16 DFT rule checkers glue design together
Advances in DFT rule checking will likely continue as more designs depend on increasingly complex testing protocols.
2010-07-29 Design flow optimizes partial reconfiguration FPGAs
Xilinx releases a streamlined design flow for its FPGAs that support partial reconfiguration and offer on-site programming and re-programming.
2006-10-16 Achieve low-power design success at 65nm
Tom Chau and Cheng Shi compile tips for designers to ensure success for advanced low-power designs at 90nm and 65nm.
2008-05-09 Run practical power network synthesis
Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools
2002-09-16 Power-savvy design will rule IC world
IC designers on the leading edge are quickly coming to realize that power and its many effects have begun to pose the top design challenge in the nanometer realm.
2008-06-24 Low power design for analog/mixed-signal IP
Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must be considered early in the design phase.
2012-12-07 Synchroniser with programmable MTBF capabilities
Here's a high frequency synchroniser circuit with programmable mean-time-between-failure capabilities well suited for high frequency clock gating and input signal synchronisation applications.
2012-02-29 Designing high frequency synchronizer with programmable MTBF features
Read about a high frequency synchronizer circuit with programmable mean-time-between-failure capabilities that is well suited for high frequency clock gating and input signal synchronization applications.
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