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2005-05-09 New MUX from Micrel prevents runt pulses during switchover
The SY89844U from Micrel is a low jitter LVDS, 2:1 input multiplexer designed for redundant source switchover apps.
2005-05-27 Micrel MUX prevents runt pulses
The SY89845U precision CML runt pulse eliminator (RPE) 2:1 MUX from Micrel features a 1:2 fanout and internal termination
2002-07-03 Micrel clock buffers provide ultra-low skew, jitter, redundant switchover
sy89830u, sy100ep15v, pecl, lvpecl, clock fanout buffer, sonet, sdh, communication system
2002-02-05 LSICSI clock converters feature x4 resolution
LSI Computer Systems Inc. has released the LS7183 and LS7184 quadrature clock converters that feature x1, x2 and x4 resolution
2005-02-16 IRIG-B clock time-stamps digital delay generator data
Interface Technology is now announcing immediate availability of its IRIG-B Real Time Clock option for the DDG200 and DDG400
2010-04-20 A/V clock generator delivers 40ps jitter
National Semiconductor has released a triple-rate audio/video clock generator that eliminates the need for external clock conditioning in professional and broadcast video equipment
2005-03-30 Failsafe' clocking mechanism offers clock switchover
Micrel's new clock multiplexer ICs feature runt-pulse elimination and Fail Safe Input circuitry
2002-10-16 Flexible timing key to CCD design
CCD's performance depend on timing generator, which produces a variety of clock pulses to determine how image is acquired and reconstructed.
2016-03-17 Achieve picosecond precision with FPGA techniques
When dealing with digital converters implemented on FPGA, you need to take important features into consideration to reach picosecond precision.
2007-02-05 Output of three-phase PWM signals and the corresponding inverse signals
This article describes how high-level width of pulses is controlled to manipulate the duty cycles of pulse-waveform signals, a technique to produce three-phase pulse-width modulation signals and the corresponding inverse signals
2005-11-17 Network-transparent modules implement remote JTAG testing
JTAG Technologies' TapCommunicator makes it possible to execute boundary-scan tests on targets with test-clock frequencies of up to 40MHz, over an unlimited distance, across asynchronous network paths
2014-05-05 VadaTech kits out MCH with 40GbE option, advanced clocking
The MCH boasts up to four times boost in performance and enables highly flexible master/slave clock and time synchronisation to multiple clocking standards, leading to precision timing, aligned frequency/phase of the signals, and risk elimination involving packet loss due to buffer overflow
2007-07-23 Telecom timing chip enables 1G, 10G SyncE
Maxim's DS3104 chip is said to be the industry's first to provide full carrier-class clock synchronization for new Synchronous Ethernet line cards and mixed SONET/SDH/SyncE line cards
2008-03-07 Stratum 3 timing-card IC supports SyncE
Maxim has introduced the DS3102, said to be the industry's first timing-card IC to provide full carrier-class, Stratum 3 clock synchronization for G.8262-compliant synchronous SyncE equipment
2005-04-05 Oscillator tailored for portable apps
The LTC6906 programmable silicon oscillator with an operating current of 18?A at 100kHz from Linear Tech is touted to be the ideal clock chip for portable equipment
2011-10-21 Optoencoder touts small 7 x 8mm board space
The iC-LNG device can deliver clock rates of up to 16MHz for cycle times of less than one microsecond
2014-05-21 Divide by N to synchronise DC/DC converter clocks
Find out how to utilize a clock divider for producing differently-phased clocks for clocking the converters found in automotive power conversion solutions
2007-07-24 Board synchronizes 2GHz A/D processing modules
Pentek Inc. releases its Model 6890, a 2.2GHz clock, synch and gate distribution board for synchronizing multiple Pentek I/O modules
2011-08-04 AFGs offer up to 350MHz in single, dual channels
The Wave Standard AFG models boast a 2GS/s clock, 14bit, 512Kpoint arbitrary waveforms and up to 4Vp-p into 50 output amplifier
2011-10-14 Reduce yield fallout by avoiding over and under at-speed testing
Here's a look at the problems associated with SoC at-speed testing such as overtesting and under-testing. This article also provides suggestions on how to overcome them.
2005-07-15 New bus buffers from Linear Tech
Linear Tech's new bus buffers promise to solve the common problem of a stuck bus by isolating all of the bus connections on the upstream side, while restoring the downstream bus
2006-12-21 I?C bus buffer enhances system reliability
Linear Technology has introduced an I?C bus buffer with low offset and stuck bus recovery that increases the reliability of systems using the I?C bus.
2014-09-24 Designing UART in MyHDL and testing it in FPGA
In this article, we will learn how to capture our very own universal asynchronous receiver/transmitter design using MyHDL, a free, open-source Python library.
2010-07-02 Calculating the tachometer register value of the MAX6615/MAX6616
This application note explains how the MAX6615/MAX6616 temperature monitors and fan-speed controllers calculate the tachometer register value. The relationship between tachometer resolution and fan speed is also discussed.
2003-11-11 Zarlink TDM family eases board-level design
The company has launched a family of mid-density TDM switching devices that simplifies board-level design.
2003-04-16 Zarlink packs timing module into 2.54-by-2.54mm DIL package
The ZL30462 timing module from Zarlink Semiconductor Inc. integrates a complete timing system into a 40-pin DIL package measuring 2.54-by-2.54mm.
2004-11-16 WLANs are jump-starting cognitive radio
CR techniques can be expanded in an evolutionary way to achieve the full promise of wireless communications.
2015-04-27 Verilog-AMS vs SPICE view for SoC verification
In this article, we comparatively analyse the usage of Verilog/Verilog-AMS and SPICE views from the perspective of data converters and clocking IPs in an SoC.
2008-02-18 Use UWB in ultralow-power Zigbee sensor nodes
The IEEE 802.15.4 standardization committee who defined the MAC and PHY adopted by Zigbee has proposed an alternative PHY relying on UWB technology.
2009-05-25 Transferring arbitrary waveform data to the 33200A family of function/arbitrary waveform generators
This application note reviews three methods of transferring arbitrary waveform data to 33200A function/arbitrary waveform generators: front panel, Agilent IntuiLink Waveform Editor and programming.
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