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2006-01-26 Synthesis tool combines advantages of flat, hierarchical design
It's one thing to design individual blocks for large systems-on-chip and another to tie them together into a working device. Sierra tackles the latter challenge with its Pinnacle Chip Assembly solution.
2013-05-23 Performing synthesis-aware clock analysis
Read about a tool that performs clock structure analysis by tracing complex clock nets and visually presenting them to designers
2006-07-12 Clock implementation tool supports 65nm design flows
Azuro said version 3 of the PowerCentric clock implementation solution provides 15 percent to 25 percent power reduction to support advanced variability-aware design flows at 65nm and below
2011-07-14 Cadence buys clock optimization tech company
Cadence hopes to address SoC performance, power and area challenges with the acquisition of Azuro and its clock optimizing technology
2016-04-27 Clock line-up targets 100G/400G optical transceivers
Silicon Labs' Si534xH coherent optical clocks replace discrete timing solutions that rely on expensive, large-footprint VCSOs to provide low-jitter reference timing for data converters.
2014-11-28 Boost data rates with clock generators
To meet the intensifying demands for higher data rates, high-speed networking and data centre equipment calls for frequency-flexible clock generator IC solutions to support faster data rates
2003-05-30 ASICs added to Synplicity's synthesis line
Synplicity Inc. will expand into ASIC physical synthesis with a tool that competes against offerings from Synopsys, Cadence and Magma
2012-04-03 Developing NAND flash controller with high-level synthesis
Read about the application of a commercial HLS tool to a NAND flash controller with an error correction code block.
2009-02-26 65nm FPGAs, clock ICs defy downturn
Seeking to grab share in a down market, Lattice has introduced its first 65nm FPGAs in the market and has expanded its family of differential clock distribution ICs. It also announced the availability of 15 new reference designs and a new development kit for its MachXO PLD family
2005-04-18 Synopsys unveils 'next-gen' compiler
The company introduces a physical design solution which it says provides concurrent clock tree synthesis, routing and yield optimization.
2003-10-01 SynApps customizes its tools for users
Following an unusual business model, SynApps Software Corp. leverages in-house technology to offer customized EDA tools that perform static timing analysis, synthesis, placement, clock tree synthesis and simulation.
2007-05-30 Routing suite receives 45nm design update
Gearing up to deal with 45nm IC physical design challenges such as interconnect resistance, Sierra Design Automation Inc. this week is announcing three significant enhancements to its Olympus-SoC placement and routing suite.
2006-07-07 Power reduction tool from Azuro extends to 65nm
Azuro has released version 3 of its PowerCentric low power clock implementation tool, which extends the company's power reduction capabilities to support advanced variability-aware design flows at 65nm and below
2000-12-01 Integrated approach for emerging tech designs
This technology article describes the integration of clock tree synthesis with logic synthesis, placement route and interconnect extraction to maximize the potentials of cell-based designs.
2010-10-14 GN ReSound adopts Magma Talus for hearing solutions
According to Magma Design Automation, hearing instrument solution maker GN ReSound has selected the Talus implementation system for its next-generation ICs.
2014-11-06 Enhance SoC efficiency with multi-bit flip-flops
Here's a look at the architecture of multi-bit flip-flops, its merits and drawbacks. It also tackles the results of its implementation in a particular design and the various areas of concern.
2013-08-27 Achieve successful timing closure
Find out how to derive design margins for successful timing closure.
2005-03-30 'Concurrent' IC design suite rolls
Synopsys rolled out IC Compiler, which concurrently runs physical synthesis, clock tree synthesis, placement, routing, yield optimization and signoff correlation.
2004-03-17 Tool pinpoints false paths, steers designers away
FishTail Design Automation is targeting what sounds like a small niche, but the company says the potential benefits of its technology are huge.
2014-12-09 Reduce power SoC consumption in the interconnect
Here's a modular approach to SoC interconnect for reducing power consumption. The modular concept is different because it consists of a distributed architecture of various components.
2008-02-19 PICO Extreme platform touts TCAB technology
A breakthrough in algorithmic synthesis technology has been announced by Synfora Inc. The company claims its PICO Extreme platform automatically creates complex hardware sub-systems (application engines) from sequential untimed C algorithms
2004-06-09 Incentia releases runtime QOR for tool line
Incentia Design Systems released the 2004.05 version of its timing analysis, logic synthesis and physical synthesis software products
2006-10-16 Achieve low-power design success at 65nm
Tom Chau and Cheng Shi compile tips for designers to ensure success for advanced low-power designs at 90nm and 65nm.
2011-09-01 Speeding up medical imaging process using FPGA
Read about the use of FPGA platform and a synthesis tool called Impulse C to speed up a statistical line of reaction estimation for a high-resolution PET scanner
2015-01-28 Performing automatic ASIC-to-FPGA conversion
Performing ASIC-to-FPGA clock tree conversions by hand is hard and time-consuming for designers, but the use of automated gated clock conversion makes this task much less challenging
2012-06-29 Reference flow pushes low power design
Synopsys' 40nm SMIC-Synopsys RTL-to-GDSII version 5.0 reference design flow features automated clock mesh synthesis and a gate array engineering change order flow
2001-05-01 Vendors should count silicon, not tapeout wins
Tapeouts are certainly important. But they are not an end unto themselves, but, rather a milestone on the way to the goal of working silicon.
2008-06-05 TSMC stirs IC designs using 40nm node
Paving the way for next-generation chips, TSMC is set to roll out its latest design methodology for IC production at the 40nm node.
2005-03-17 Synopsys unveils 'next-gen' compiler for physical design
Synopsys unveiled a physical design solution, which the company claims provides leading-edge performance and already carries endorsements by key IC suppliers.
2008-10-06 Synopsys heralds 2-3x speed boost with IC Compiler release
Claiming a 2X to 3X speed-up in overall design turnaround time compared to the previous release, Synopsys Inc. introduced last week the IC Compiler 2008.09.
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