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2014-09-19 Online tool eases clock tree design for Internet infrastructure
The Clock Tree Expert tool from Silicon Labs allows embedded developers to generate sophisticated, streamlined clock tree block diagrams, reducing BOM count and speeding time to market.
2007-03-05 Magma tools cut clock tree power draw by 25%
Magma Design Automation has introduced a pair of low-power IC implementation and analysis tools that the company claims have been shown to reduce power consumption in nanometer ICs by 25 percent.
2001-03-21 Delta39K PLL and clock tree
This application note provides information and instruction in utilizing the functionality of the Delta39K PLL and associated clock tree.
2005-04-18 Synopsys unveils 'next-gen' compiler
The company introduces a physical design solution which it says provides concurrent clock tree synthesis, routing and yield optimization.
2003-10-01 SynApps customizes its tools for users
Following an unusual business model, SynApps Software Corp. leverages in-house technology to offer customized EDA tools that perform static timing analysis, synthesis, placement, clock tree synthesis and simulation.
2004-04-02 Sequence claims key optimization patents
Sequence Design has announced four new patents that cover key analysis and optimization technology, according to the company.
2007-05-30 Routing suite receives 45nm design update
Gearing up to deal with 45nm IC physical design challenges such as interconnect resistance, Sierra Design Automation Inc. this week is announcing three significant enhancements to its Olympus-SoC placement and routing suite.
2014-12-09 Reduce power SoC consumption in the interconnect
Here's a modular approach to SoC interconnect for reducing power consumption. The modular concept is different because it consists of a distributed architecture of various components.
2013-05-23 Performing synthesis-aware clock analysis
Read about a tool that performs clock structure analysis by tracing complex clock nets and visually presenting them to designers.
2006-09-01 Optimizing DSPs for multimedia
With the aid of new design techniques, DSP designers can now address the main areas of power consumption--leakage power, clock trees, logic transitions and power grids.
2003-03-10 LCK4953 Low-Voltage PLL Clock Driver
This application note describes the LCK4953, a PLL-based clock driver device intended for high-performance clock tree designs.
2010-10-14 GN ReSound adopts Magma Talus for hearing solutions
According to Magma Design Automation, hearing instrument solution maker GN ReSound has selected the Talus implementation system for its next-generation ICs.
2015-11-19 Detect corner-case issues with post-silicon testing
Here is a look at the various areas identified for post-silicon stress tests on automotive SoC to enable early detection of system level issues.
2013-08-27 Achieve successful timing closure
Find out how to derive design margins for successful timing closure.
2008-10-01 Tech advancements need new routing architecture
State-of-the-art routing technology is now required to handle complex design rules and to trade-off yield and other design goals efficiently at advanced process nodes. It must be variation-aware and fully integrated with placement, clock tree, and multi-corner multi-mode optimization in order to achieve higher QoR.
2015-01-28 Performing automatic ASIC-to-FPGA conversion
Performing ASIC-to-FPGA clock tree conversions by hand is hard and time-consuming for designers, but the use of automated gated clock conversion makes this task much less challenging.
2000-12-01 Integrated approach for emerging tech designs
This technology article describes the integration of clock tree synthesis with logic synthesis, placement route and interconnect extraction to maximize the potentials of cell-based designs.
2002-04-08 FPGA clock trees and their efficient use
This article provides description on the features of proASIC and proASICPlus' clock tree as well as its design issues and applications.
2000-08-30 Clock buffer cell user guide
This application note explains how to instantiate and connect one or more clock buffer cells, and how to achieve an acceptable routing of the associated clock tree.
2005-03-30 'Concurrent' IC design suite rolls
Synopsys rolled out IC Compiler, which concurrently runs physical synthesis, clock tree synthesis, placement, routing, yield optimization and signoff correlation.
2004-07-28 VIA highlights design challenges at 90nm
The escalating design costs and complexities have been the greatest challenges for the small and medium sized IC design houses when migrating to deep submicron technologies.
2004-07-28 VIA highlights design challenges at 90nm
The escalating design costs and complexities have been the greatest challenges for the small and medium sized IC design houses when migrating to deep submicron technologies.
2001-05-01 Vendors should count silicon, not tapeout wins
Tapeouts are certainly important. But they are not an end unto themselves, but, rather a milestone on the way to the goal of working silicon.
2007-03-16 Use CT delta-sigma ADCs to cut down power consumption
Continuous time delta-sigma ADC technology shatters the conventional wisdom that pipeline ADCs are the only conversion technique available for high-speed, dynamic range applications.
2008-06-05 TSMC stirs IC designs using 40nm node
Paving the way for next-generation chips, TSMC is set to roll out its latest design methodology for IC production at the 40nm node.
2004-03-17 Tool pinpoints false paths, steers designers away
FishTail Design Automation is targeting what sounds like a small niche, but the company says the potential benefits of its technology are huge.
2014-07-31 Timing IC integrates clock generators, jitter attenuators
The chips provide an I2C-configurable platform featuring a combination of frequency translation capabilities and
2005-06-07 Three tout more nimble physical design
Three tool vendors are pitching breakthroughs in IC physical design in advance of next week's Design Automation Conference
2013-12-23 The lowdown on high-perf timing in board design
Know the various scenarios facing board designers when working with high-performance timing.
2015-04-30 Taking advantage of TSMC's 28HPC process
Here are five areas where designers can take advantage of this new process with logic library technology to optimise the performance, power and area of their system on chips.
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