Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > cmos scaling

cmos scaling Search results

?
?
total search267 articles
2005-06-17 TI outlines further CMOS scaling
Texas Instruments Inc. (TI) is presenting papers that describe key accomplishments on advanced materials and manufacturing process development at the 2005 Symposium on VLSI Technology.
2010-06-28 Stanford top engineer weighs in on CMOS outlook
i>EE Times recently sat down with James Plummer, dean of Stanford's school of engineering, for a wide ranging interview on the outlook for CMOS, engineering, education and globalization
2002-02-12 Scaling debate stalks chip conference
From the wide range of panels and tutorials at the International Solid-State Circuits Conference, from the myriad papers, from the conversations in the hotel halls, a single gnawing issue grew from hints and whispers to a groundswell of concern: Will IC technology continue to scale?
2011-05-30 NVIDIA joins IMEC's advanced CMOS scaling program
NVIDIA signed a 3-year research collaboration agreement with IMEC's advanced CMOS scaling program, enabling it to get insight about future design technology options on its next-generation products.
2002-06-19 Materials transitions stalk CMOS scaling
With the transition to copper and low-k interconnects showing just how difficult changes in materials can be, technologists gathered at the Symposium on VLSI Technology to consider a brace of materials challenges?ranging from new gate oxides to SOI and strained-silicon channels.
2012-03-15 Imec, Riber continue team up on next-gen III-V CMOS
Through the collaboration with Riber, Imec can integrate the power of UHV-systems into state-of-the-art semiconductors production equipment on large diameter wafers.
2011-05-31 Imec, Altera collaborate for advanced CMOS scaling program
Altera will work together with Imec through a three-year research collaboration to develop advanced CMOS scaling program. Initially, they will focus on 3D process technology development.
2007-10-17 IMEC extends CMOS scaling research to DRAM MIMCAP
IMEC announced it has initiated research on next-generation DRAM MIMCAP process technology as part of its (sub-)32nm CMOS device scaling program.
2008-10-06 For now, CMOS is still irreplaceable
Dennis Buss, chief scientist at TI, gave a retrospective look and a prospective analysis of the semiconductor industry as Moore's law is expected to stagnate toward the end of the next decade.
2014-07-17 Exploring next-gen CMOS: Moving towards application
An Imec fellow is looking at many ideas floating around CMOS that can be tested and tried out, and see if they can be put to use and if a technology can be built from them
2004-01-14 Europe plans mega funding for nano CMOS
The European Commission (EC) has approved the first phase of a proposed multiyear collaborative research program to advance CMOS beyond the 45nm node
2006-08-16 CMOS scaling: painstaking but possible
CMOS scaling is, in fact, proving to be a painstaking and humbling taskalbeit a possible one.
2010-03-24 CMOS ADC handles 127Gbit/s PM-QPSK scheme
Opnext Inc. has developed a low-power quad CMOS ADC, designed for use in a 127Gbit/s Polarization Multiplexed Quadrature Phase Shift Keying (PM-QPSK) modulation scheme
2008-06-23 Toshiba compact model ups gate density in 45nm CMOS
Toshiba Corp. has developed a new compact model for circuit design that achieves higher gate density and improved cost-performance in next-generation 45nm CMOS technology
2003-12-11 TI's SETMOS said to extend CMOS life
Texas Instruments Inc., together with researchers at the Swiss Federal Institute of Technology of Lausanne and the U.S Air Force Research Laboratory, have described a potential way to use single electron transistors (SETs) to perform logic functions.
2012-07-04 The CMOS-mobile apps connection
The two biggest markets for logic chips are, of course, mobile (smartphone and tablet) and PC devices. These markets are now steering the technology direction and defining the winners and losers.
2014-01-03 Temperature sensors target advanced CMOS tech
Moortec unveiled what it describes as an improved range of on-chip temperature sensors with an uncalibrated accuracy of ±3°C and a calibrated accuracy of ±1°C, from -40°C to 125°C
2004-05-07 Scaling dead at 130nm, says IBM technologist
The traditional scaling of semiconductor manufacturing processes died somewhere between the 130nm and 90nm nodes, Bernie Meyerson, IBM's CTO, told an industry forum
2013-04-17 Research: Layered 2D nanocrystals to replace CMOS
Made up of a material called molybdenum disulfide, the layered structure could pave the way for further scaling and improving compute performance driven by smaller transistors
2013-01-30 Qualcomm, Imec team up on CMOS advancement
Geared to accelerate scaling technologies for logic and memory devices, the organisations extended their collaboration in charting roadmaps for next-generation products
2012-02-23 PCM progress report no. 5: Scaling issues
Learn about the possible approaches to achieve the scaling necessary to make PCM a commercial success
2016-04-07 Moore's Law extended: Intel roadmap reveals CMOS at its core
Intel's future processors at 10nm and beyond will continue to use CMOS, but the cores will be surrounded by novel circuit architectures using new materials that may extend Moore's Law indefinitely
2006-05-25 Micron plans to double CMOS sensors production
Micron Technology intends to double its CMOS sensor manufacturing capacity by converting two memory fabs to imager chip production
2012-06-08 Intel finFETs show variability, need SOI for scaling
GSS has concluded that Intel may need to turn to SOI wafers to scale its FinFETs below 22nm, which may have implications for foundries that are yet to introduce FinFET technology into their chip manufacturing processes.
2005-10-24 IMEC proposes sandwich substrate to extend CMOS era
Researchers at IMEC have proposed that multi-layer substrates comprised of gallium arsenide grown over germanium grown above silicon, together with novel gate dielectrics and metal gates, could be the best way to extend the use of CMOS into the sub 45nm device era
2006-06-14 Freescale demonstrates CMOS tech with strained SOI substrates
Freescale Semiconductor demonstrated an advanced CMOS technology that utilizes strained silicon-on-insulator substrates that could deliver dramatic performance improvements
2009-02-12 Five ways to beat IC scaling roadblocks
Intel senior fellow and director of process architecture Mark Bohr listed five major stumbling blocksor challengesfor the 32nm node and beyond.
2011-06-20 FinFET outperforms planar CMOS
In a test comparing impact of process variability, Imec has found out that FinFET technologies emerge superior than planar CMOS, with results allowing creation of better technology and higher yields
2010-02-10 Expert: Graphene will drive post-CMOS era
The winner in the post-CMOS era has not been declared yet, but graphene holds great promise, said James Mexindl, director of the Joseph M. Pettit Microelectronics Research Center
2011-06-08 CMOS platform cuts power use by 50
SuVolta Inc. develops a new energy-saving CMOS platform which promises at least 50% cut in power use
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top