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complex programmable logic device What is a complex programmable logic device (CPLD)? Search results

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What is a complex programmable logic device (CPLD)?
A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. It is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections.
total search189 articles
2005-07-22 New programmable device family combines CPLD, FPGA features
Lattice Semiconductor introduced MachXO, a new product family that combines the key features of complex programmable logic device (PLD) and FPGA technologies in a single device.
2005-08-18 How to integrate Flash device programming and reduce costs
Flash memory devices offer great value to engineers who seek high-density, low-cost memory devices that are easy to program and erase.
2002-10-30 Xilinx offers IQ solutions for programmable IC devices
Xilinx Inc.'s two new additions to its IQ Solutions line is specifically targeted for the automotive telematics market.
2003-05-13 Lattice rolls out PCB power management device
Lattice Semiconductor has announced the release of the Power604 device, which provides a complete solution for PCB power sequencing
2002-07-16 Lattice lands programmable-logic combo punch
Lattice Semiconductor has announced a new architecture that combines the programming attributes of CPLDs and FPGAs.
2002-12-06 Implementing an SDRAM controller in a Lattice ispLSI device
This application note discusses how to implement an SDRAM controller using an ispLSI CPLD.
2001-03-01 Flow is shaky for programmable SoCs
Programmable SoC designs are becoming the trend of the future thanks to the greater density of today's programmable devices and the availability of efficient microprocessors. Unfortunately the CAD flows for these devices are far from being robust
2002-12-06 A 32x32 Crossbar switch implementation using the Lattice ispLSI 5384VE device
This application note discusses how to implement a 32x32 crossbar switch using the ispLSI 5384VE CPLD.
2015-03-24 Top 5 problems with programmable logic controllers
PLC's duties are crucial for complex processes. However, like most things in life, they can be both advantageous and disadvantageous. Read this article to discover what can possibly go wrong
2000-03-01 Taking new stabs at programmable analog
Programmable logic has some traditional advantages over ASIC design. The gate count of FPGAs approaches that of custom circuits. FPGAs can be programmed?and re-programmed?out in the field, enabling fast time to market. ASICs, in comparison, need careful attention to layout and fabrication technology. It can take anywhere from six weeks to two years (depending on the complexity of the circuit) to get an ASIC working properly
2014-02-14 Taking a look at the field-programmable RF chip
Developed in the US for UK's Lime Microsystems, the FPRF transmitter takes a digital data stream and converts it into wireless signals, while the receiver performs the inverse operation.
2008-04-21 Synplicity tips device-independent FPGA design tool
A device-independent IP configuration and system-level assembly environment has been introduced by Synplicity
2001-05-01 Programmable system chips move forward
Using dedicated hardware to boost real-time performance of embedded systems is a common practice and, with the introduction of PSCs, software engineers will learn how to boost performance of timing-critical software functions.
2005-03-30 Mixed signal power control is programmable and non volatile
The analog inputs of Lattice's new Power1208P1 device are capable of monitoring power supplies with voltages down to 0.67V
2005-08-08 Introduction to Programmable Systems-on-a-Chip
There are a variety of programmable SoCs complete with underlying architectures and technologies. Tradeoffs exist between different programmable SoC devices
2002-03-01 Integration trends in programmable logic
This news article illustrates the integration issues of programmable logic devices with other system functionality to drive PLDs in ASIC applications
2014-03-12 Examining field-programmable RF chip
Here's a look at a chip that comes from the wireless domain and is touted to bring exciting new possibilities.
2014-04-08 Domain-specific languages for medical device design
Learn how existing languages for PLCs can be extended with domain-specific constructs.
2007-04-16 Using logic-optimized FPGAs in displays
Image quality in FPDs is highly subjective, and image-enhancement algorithm specifications continue to evolve. As a result, low-cost, logic-optimized FPGAs and reference designs enable designers to modify image-enhancement algorithms quickly and easily
2002-11-20 Implementing a High Performance Pipelined Multiplier in a Lattice ispLSI5512VE Device
This application note describes some of the techniques available for performing high-speed signed multiplication in a Lattice ispLSI 5512VE-80LF256 device
2002-11-14 Xilinx offers CPLD design kit for free
Xilinx Inc. is offering the CoolRunner-II Design Kit to qualified customers for free to further strengthen the emerging CPLD market.
2002-07-05 Xilinx ICs target automotive telematics industry
Xilinx Inc. has announced the IQ series of FPGA and CPLD products that are targeted specifically for the automotive telematics industry.
2006-06-20 Xilinx CPLDs adopted in Sharp handsets
Xilinx announced that Sharp has adopted Xilinx's CoolRunner-II CPLDs for Sharp's W-ZERO3 series of mobile information handsets.
2002-01-16 Xilinx axes analog to cool CPLD power consumption
Xilinx Inc. believes that CPLDs in their current form about to reach the end of the road, and says the only way to keep scaling them linearly is to get rid of power-hungry analog circuitry.
2000-06-29 XC9500 CPLD power sequencing
This application note describes the underlying XC9500 circuitry to give designers the understanding they need to best use these powerful CPLDs.
2000-06-28 Using serial vector format files to program XC9500 devices in-system on automatic test equipment and third party tools
This application note describes how to program XC9500 devices in-system, using standard serial vector format (SVF) stimulus files.
2001-03-23 Using IEEE 1149.1 boundary scan (JTAG) with Cypress Ultra37000 CPLDs
This application note provides an overview of the Boundary Scan Test (BST) implementation in the Ultra37000 CPLDs, and shows how to connect the devices in the JTAG chain for BST as well as ISR operations.
2001-03-22 Using FIFOs in Delta39K CPLDs
This application note provides instructions for all aspects of implementing synchronous FIFO buffers in Cypress Semiconductor's Delta39K CPLDs, such as description of FIFO operation, static timing analysis, etc.
2001-03-23 Using Cypress CPLDs in mixed-voltage systems
This application note explains how the FLASH370i and Ultra37000/37000V CPLDs can interface with different logic families in a mixed 3.3V and 5V environment
2000-06-28 Understanding XC9500XL CPLD power
This application note discusses the XC9500XL CPLD power estimation and optimization. The paper provides the reader with an understanding of sense amplifier-based CPLD power dissipation.
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