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2010-01-13 Targeting small delay defects
To maintain the quality of test for the reasonable DPM levels, more and more test engineers are looking to target small delay defects with ATPG
2011-08-30 Optical delay lines to fit into a computer chip
Researchers from the Joint Quantum Institute and Harvard University are proposing an optical delay line that could fit into a computer chip
2009-02-26 Firms gear for EUV litho despite tool delay
ASML Holding NV has slightly delayed the delivery schedule for its "pre-production" extreme ultraviolet (EUV) lithography tool by a quarter or so.
2010-02-26 EUV delay forces tool makers to check other options
EUV lithography is delayed again and is now targeted for chip production at the 16nm half-pitch node, leaving the industry to face the dreaded double-patterning or some variation of the technology.
2006-06-16 Low-power IC test can be trying
For designers, power management means controlling leakage power lost during standby mode and dynamic power consumption when multiple transistors switch in unison to perform desired functions.
2015-02-11 Detect physical defects using advanced fault models
Here is a look at the use of advanced fault model for detection of physical defects that cannot be detected using conventional Single Stuck-at and Transition Fault models.
2006-12-12 Cadence, Advantest ink car electronics testing partnership
Cadence Design Systems and Advantest Corp. announced a collaborative partnership to deliver a methodology for zero-defect testing of digital automotive electronics
2004-08-16 AC scan needed for nanoscale device testing
AC scan offers a number of key advantages over DC scan and other traditional functional test approaches.
2005-01-03 Test experts ponder cost of defects
Is 100 DPPM too tough to be practical for designs in 100nm or finer processes?
2013-10-28 Performing hardware/firmware co-design (Part 1)
Know some of the best practices developers can use to boost their design’s performance. Part 1 focuses on event notification.
2006-10-19 IC firms collaborate with Synopsys to validate new ATPG tech
Synopsys has collaborated with several semiconductor firms to test a new ATPG technology designed to increase the quality of manufacturing tests by targeting small delay defects
2015-01-19 Guidelines boost test quality in advanced CMOS nodes
The best way to achieve high defect coverage is to apply tests other than the conventional stuck-at and transition tests. Here's a list of the guidelines that help improve test quality
2008-02-13 Camera phones get smarter with ST's image sensor
ST's latest technologies in pixel-defect correction, adaptive-noise reduction and sharpness enhancement ensure that its new camera sensor delivers outstanding image quality
2006-01-26 Mentor, STARC ink IC design agreement
Mentor Graphics announced a joint development agreement with STARC, a research and development consortium co-founded by eleven major Japanese semiconductor companies.
2007-10-29 ATPG offers improved low power management
Synopsys has expanded the low power management capabilities in its Galaxy test solution reduce the time and effort needed to generate high-quality, power-aware manufacturing tests for ICs.
2004-02-02 Traveling at memory speed
The combination of a memory BIST engine with enhanced at-speed application provides the basis for ensuring high-quality testing of SoC designs with embedded memories.
2014-09-04 Thwarting IoT security threats with ARM TrustZone
Virtualisation can be leveraged to enable consolidation of connected devices, and ARM TrustZone can be utilised to tackle security threats to the Internet of Things.
2005-02-14 SRAMs readied for 45nm node
Issues like soft errors and gate current leakage are emerging as design challenges as SRAM technology moves below 90nm, according to memory experts at this week's International Solid-State Circuits Conference here.
2009-12-15 Silicon tuner supports all TV standards
Silicon tuners are poised to replace traditional MoPLL based CAN tuners in all applications, and NXP's new tuner fits in all TVs.
2004-05-04 Production tester addresses high-speed serial chip tests
Agilent claims its high-speed production tester is the industry's first for identifying the maximum number of product defects at the lowest cost.
2012-12-12 Perform efficient debug of multi-core MCUs
The real challenge is the processing of the high quantity of debug information coming from all cores and its proper presentation in real-time on the developer's screen.
2007-10-08 Mentor upgrades TestKompress for 65/45nm nodes
By providing compression levels exceeding 100X, the new TestKompress Xpress technology allows IC manufacturers to meet challenging quality objectives for advanced process nodes at 65nm and beyond without driving up the cost of testing.
2003-08-18 Memory overwhelms current verification techniques
Circuit simulation is unable to provide adequate functional verification coverage for memories.
2005-06-08 LogicVision product to address nanometer design challenges
LogicVision announced an embedded test solution to tackle the increasingly difficult challenges associated with nanometer design and test
2012-08-09 Improve SoC yields with diagnostic and repair tools for embedded memory
Learn about embedded memory test solutions, including fault detection in very deep submicron technologies, repair at the manufacturing level, as well as diagnosis for process improvement and field repair capabilities.
2005-01-17 Good bridge testing needed
Combating bridging defects becomes prevalent as chip design processes continue to shrink from 90nm below.
2013-09-27 Enable depth discernment in embedded vision apps
Explore the depth sensor technology alternatives available for building vision applications with the ability to sense objects in three dimensions.
2005-10-11 DFM delays 90 and 65nm, analyst says
Design for manufacturability (DFM) concerns have slowed the ramp-up of 90nm wafer volumes and will be even more problematic at 65nm, said Handel Jones, CEO of International Business Strategies Inc., at the Fabless Semiconductor Association Expo Thursday (Oct. 6).
2007-04-24 Data-management platform enables scalable, collaborative IC design
IC Manage has announced Global Design Platform (GDP), said to be the first data-management solution to offer design assembly, derivative management and real-time worldwide delivery.
2016-05-02 Data inspection techniques for massive memory designs
Learn about efficient data inspection techniques that will help you reduce the verification stint in a large storage high bandwidth DDR-based memory design.
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