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2003-09-10 Xilinx upgrades ISE FPGA design suite
Xilinx Inc. has improved clock performance, software run-time and area utilization in its Integrated Software Environment FPGA design suite
2006-07-07 Xilinx unveils design tools for 65nm Virtex-5 FPGAs
Xilinx has announced the latest release of its design solution, the 8.2i ISE tool suite, now supporting the company's newest line of 65nm Virtex-5 domain-optimized FPGAs
2013-12-05 Xilinx outs comprehensive functional safety design package
The company's functional safety package includes a TUV SUD certified design methodology and tools that promise to increase design productivity and reduce certification risks
2008-03-26 Xilinx design tools suit logic, embedded, DSP
Xilinx has introduced its ISE Design Suite 10.1, a single unified release providing FPGA logic, embedded and DSP designers with immediate access to the company's entire line of design tools with full interoperability
2002-08-27 Xilinx design tool integrates IBM bus analyzer
Xilinx Inc. will begin shipment next month of the ChipScore Pro v5.1i logic debug and verification tool that features IBM's CoreConnect integrated bus analyzer cores, core insertion tools, and an analyzer interface.
2006-06-29 Xilinx delivers design solution for 65nm FPGAs
Xilinx has released the 8.2i Integrated Software Environment (ISE) design solution supporting the company's 65nm Virtex-5 FPGAs
2008-02-18 Why we need a new analog design flow
Analog-mixed signal designers need a first-time right design methodology now. Why is this familiar cry more urgent and probably truest this time
2005-09-16 When infrastructure is essence: Open-Silicon automates the flow
Researchers implement an automated decision and control flow that supports data as it moves through the design process.
2003-03-31 Virage supports Synopsys design platform
Virage Logic Corp. has announced that its silicon-proven product family is available for the Synopsys Inc.'s Galaxy Design Platform
2005-06-13 VIA integrates Sandwork debugging tools into IC design flow
The analog and mixed-signal debugging tools from Sandwork Design Inc. have been incorporated into the IC design flow of Taiwan-based VIA Technologies Inc.
2002-10-01 Verplex: Solutions for correct RTL design implementation
Taiwan started promoting electronics in the 1980s as part of its key economic development initiatives.
2011-02-07 Verification design flow connects third-party PCB tools
AWR has released an ODB++ PCB layout verification design flow for connecting third-party tools with its software solutions.
2015-01-07 Using sub-threshold techniques for IC design
The use of sub-threshold techniques can be a powerful way to create circuits that consume dramatically less energy than those built using standard design practices
2001-05-24 Using PrimeTime in LSI Logic's FlexStream design flow
This application note outlines the procedures LSI Logic recommends to customers on performing static timing analysis using the PrimeTime analysis tool.
2003-12-16 Using ISSP technology in structured ASIC design
NEC's ISSP technology for designing structured ASIC has become popular with design engineers because of its easy-to-use design flow and clear road map for 90nm.
2001-05-24 Using formality in LSI Logic's FlexStream design flow
This application describes procedures and recommendations for using the Formality formal equivalence checking tool for Gate to Gate equivalence checking.
2001-05-24 Using formality for RTL-to-gate in LSI Logic's FlexStream design flow
This application note describes procedures and recommendations for using the Formality formal equivalence checking tool for RTL-to-gate equivalence checking.
2010-04-26 Understanding high-level synthesis design's advantages
It is vitally important to verify the design before performing high-level synthesis, not after. It is not effective to synthesize a design that does not work
2013-02-12 UMC, Synopsys partner for design verification at 28nm
UMC selected Synopsys' IC Validator physical verification product for lithography hot-spot checking to accelerate physical signoff at 28nm.
2003-01-08 TSMC, Synopsys partner to ensure library-flow compatibility
TSMC and Synopsys Inc. have collaborated to guarantee that TSMC's internally developed Nexsys 90nm libraries are fully compatible with Synopsys' RTL to GDSII flow
2007-06-28 TSMC, Cadence team on 65nm wireless design flow
Cadence and TSMC have teamed on nanometer wireless design and produced a new TSMC 65nm RF PDK compatible with the new Cadence Virtuoso custom design platform
2013-09-20 TSMC unveils 16nm FinFET design flows, uses Cortex-A15 core
TSMC's design flows include one for the company's 16FinFET process, one customised for 16FinFET that offers transistor-level design and a 3D-IC flow for the design of vertically stacked structures.
2008-06-12 TSMC targets to unify 32nm design flow
Facing the 32nm challenge, Taiwan Semiconductor Manufacturing Co. Ltd is putting the pedal to the metal with a new design-for-manufacturing scheme
2005-06-13 TSMC releases reference design flow for 65nm processes
Taiwan Semiconductor Mfg Co. Ltd has released version 6.0 of its reference flow, the sequence of EDA tools that the world's largest foundry recommends for its 65nm manufacturing processes
2004-06-07 TSMC Reference Flow 5.0 includes Optimal tools
TSMC's Reference Flow 5.0 addresses two nanometer integrity issues that are observed at both the IC and package design levels - power closure and timing closure.
2008-04-30 TSMC IC design collaboration strategy stirs controversy
TSMC has unveiled a new and possibly controversial strategy that involves more collaboration in the early stages of the IC design process
2002-05-30 TSMC adopts Cadence's signal analysis for reference design flow
Taiwan Semiconductor Mfg Co. has adopted Cadence Design System Inc.'s CeltIC signal-integrity analysis solution for its 0.135m reference design flow.
2004-06-15 Transition to 90nm raising tough design issues
Experts delving into 90nm design and process development explored a crucial question: How will the average design team handle 90nm design
2012-05-18 TowerJazz reference design flow tips Cadence tech for power management
TowerJazz's Reference Flow 2.0 power management analog/mixed-signal reference design flow integrates power management devices with control logic.
2010-08-31 TowerJazz qualifies Magma's mixed-signal design platform
Magma's Titan software and TowerJazz's foundry technology provide mutual customers with a design and manufacturing solution that accelerates the design-to-silicon process and achieves first-time silicon success
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