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2005-01-20 Synopsys develops reference design flow with China's chip foundry
Synopsys Inc. and Grace Semiconductor Mfg Corp., an IC foundry in Shanghai, China, have jointly developed a reference design flow for Grace's 180nm processes.
2007-04-02 Synopsys design platforms support UPF 1.0
Synopsys Inc. has announced a low-power design flow that will implement the Accellera Unified Power Format version 1.0 in its IC verification and implementation products in the second half of 2007.
2005-01-14 Synopsys DC FPGA improves Tensilica prototyping design flow
Synopsys Inc. announced that Tensilica Inc. has based its FPGA prototyping design flow on its Design Compiler FPGA (DC FPGA) tool.
2005-06-21 Synopsys backs migration of analog design to OpenAccess
Synopsys Inc. has joined Si2 as a result of the company's increased presence in analog simulation.
2006-10-11 Synopsys announces new semicon design tech
Synopsys Inc. unveiled new MinChip technology that analyzes physical design complexity and identifies the smallest routable size for semiconductor designs
2002-10-04 Syncron: Web-based environment in PCB design
In the last 10 years, Taiwan has enjoyed steady growth in the semiconductor industry. Even with the current economic downturn, Taiwan continues to see the emergence of numerous (and diverse) fab-less semiconductor design companies. The IC designs coming from these businesses are taking advantage of the landmark achievements in semiconductor fabrication technology
2006-06-01 Symbolic simulation improves design output
Symbolic simulation techniques are especially beneficial when used early in the design flow, particularly during the development of simulation models and circuit designs.
2003-09-16 SVP is key technology for nanometer IC design
Examine the importance of chip-level architectural issues and the need for physical hierarchy for multi-million gate nanometer SoC design
2002-05-08 SuperH picks Avant! design solution for latest MPUs
SuperH Inc. has selected Avant! Corp.'s SinglePass-SoC design solution to implement its latest microprocessor core, the SH-5
2008-03-17 Succeed at 65nm design
A true DFM-aware environment accounts for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library, continues through implementation, analysis and optimization, and ends with sign-off verification
2009-02-10 Stratix IV design guidelines
Altera Stratix IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications.
2003-03-17 STMicro adopts Agilent RF design environment
STMicroelectronics has selected Agilent Technologies' RF design environment (RFDE) for its RF/mixed-signal IC design
2006-10-16 Startups take on analog design automation
Automating analog IC design has proven to be a tough challenge, but two EDA startups are promising to do just that with a new "analog synthesis" technology
2013-01-08 Start-up takes FPGA design to the cloud
Plunify boasts that its multiple servers accelerate design flow and the cloud provides secure design collaboration capabilities.
2004-03-01 Starc to release Starcad-21 design methodology
Semiconductor Technology Academic Research Center will release v1 of a chip design methodology that covers silicon implementation from RTL to GDSII
2007-02-15 ST adopts Synopsys compiler for ASIC design
STMicroelectronics has deployed Synopsys Inc.'s Design Compiler topographical technology in its 90nm and 65nm ASIC design flow to eliminate design iterations and streamline the overall design cycle for its internal design groups and external customers.
2006-06-09 SoC tools promise seamless SystemC-to-RTL design flow
Sonics' latest SonicsMX Smart Interconnect and SonicsStudio promise a seamless SystemC-to-RTL design flow that provides consistent SystemC or RTL versions of specific SonicsMX configurations.
2011-01-20 SoC design solution optimized for HKMG tech
Synopsys Inc. announced that it is delivering a low-power, high-performance SoC design solution optimized for the Common Platform alliance (CPA) 28nm high-k metal gate (HKMG) technology
2005-07-22 SMIC and Synopsys announce reference design flow 2.0
Synopsys Inc. and Semiconductor Manufacturing International Corp. (SMIC) said Tuesday (July 19) that they have developed a new RTL-to-GDSII reference flow based on Synopsys' Galaxy design platform and SMIC's 130nm process
2005-07-22 SMIC and Synopsys announce reference design flow 2.0
Synopsys and SMIC said they have developed a new RTL-to-GDSII reference flow based on Synopsys' Galaxy design platform and SMIC's 130nm process
2003-03-25 SMIC adopts Synopsys design platform for silicon processes
Semiconductor Mfg Int. Corp. (SMIC) has selected Synopsys Inc.'s Galaxy Design Platform as the reference flow for its deep submicron processes.
2002-08-29 SiS adopts Cadence technology for graphics IC design
Silicon Integrated Systems Corp. has standardized on Cadence Design Systems Inc.'s First Encounter, for the design of complex graphics ICs
2010-11-15 Single design solution works for PL, hardware, software
Design software vendor Altium Ltd will provide its Altium Designer
2015-03-18 Signal/power integrity device targets high-speed PCB design
The HyperLynx SI/PI tool from Mentor Graphics offers tools for pre- and post-layout signal integrity, timing, crosstalk and power integrity analysis to eliminate design re-spins
2010-06-07 Scaling custom digital layout for next-generation chip design
This article details how one digital IC design team at a large fabless semiconductor company in the consumer product market is leveraging standards-based tool interoperability to maintain the benefits of hand layout for large, performance-sensitive 40nm designs
2009-06-17 S-Touch design procedure
This application note aims to provide the system/hardware engineers enough ground knowledge to start the design of capacitive touch interface solutions with the S-Touch capacitive controller devices
2002-06-05 RTL-to-GDSII flow shows signs of maturity
The RTL-to-GDSII design flow will take center stage at next week's Design Automation Conference in New Orleans, as several vendors show new technologies intended to solidify an all-in-one flow.
2011-11-14 RTL sol'n yields ultra low-power design
The RTL Power Model predicts IC power behavior at the RTL level with consideration for how the design is physically implemented
2006-06-28 Routing solution speeds design to manufacturing
The Cadence Precision Router speeds design and manufacturing convergence for advanced mixed-signal, analog and custom digital designs
2002-05-23 Rival RF design flows get a boost
Two former software partners will square off at the Design Automation Conference next month with their respective RF IC design and simulation tools
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