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2004-11-01 Wanted: New class of engineering generalists for DFM
Symposium sees need for 'tall and fat' engineers to help 'reintegrate' IC production
2006-11-16 Valor eases design with collaborative tool
vShare will provide a centralized, scalable platform with secure access to DFM-related design information, including design reviews, design changes and manufacturing sign-off
2005-05-26 UMC adopts Synopsys i-Virtual stepper system for photomask
United Microelectronics Corp. (UMC) has adopted Synopsys Inc.'s i-Virtual Stepper system (i-VSS) for photomask inspection qualification
2013-07-18 UMC adopts Cadence's DFM flows for 28nm node
The flows address both random and systematic yield issues and incorporate DFM prevention, analysis, and signoff capabilities.
2008-06-12 TSMC targets to unify 32nm design flow
Facing the 32nm challenge, Taiwan Semiconductor Manufacturing Co. Ltd is putting the pedal to the metal with a new design-for-manufacturing scheme.
2005-06-13 TSMC releases reference design flow for 65nm processes
Taiwan Semiconductor Mfg Co. Ltd has released version 6.0 of its reference flow, the sequence of EDA tools that the world's largest foundry recommends for its 65nm manufacturing processes
2012-10-11 TSMC releases 20nm, CoWoS design reference
The silicon-validated CoWoS Reference Flow enables multi-die integration to support high bandwidth, low power and can achieve fast time-to-market for 3D IC designs
2007-07-16 TSMC pulls curtains off 45nm design process
Taiwan Semiconductor Manufacturing Co. Ltd unveiled its latest and most ambitious design methodology for IC production at the challenging 45nm node.
2004-06-15 Transition to 90nm raising tough design issues
Experts delving into 90nm design and process development explored a crucial question: How will the average design team handle 90nm design
2009-01-06 Top 15 challenges to conquer for 22nm
What are the big challenges involved at the 22nm node?
2005-10-19 Tool suite 'lays foundation' for extending TCAD to DFM
Synopsys introduced early this week a new TCAD tool suite that integrates features of former TMA and ISE products as well as adding new capabilities that enable TCAD to be used in the manufacturing space
2006-11-01 Tool reduces need for immersion at 45nm
Invarium Inc. offers patterning-synthesis software promising, among other things, to limit the number of advanced layers that will require immersion at 45nm. This will allow customers to get more mileage out of existing lithography equipment.
2005-06-09 TI sticks with Synopsys for 65nm, 45nm nodes
Texas Instruments Inc. has decided to extend its use of design-for-manufacturing EDA tools from Synopsys Inc. to the 65nm manufacturing process node and has selected two Synopsys technology CAD tools for use at the 45nm node, Synopsys said
2015-11-20 Test active optical cables during design, production
Testing and analysis done at critical junctures during the design process can further reduce costs by optimising the design for high yield given specified manufacturing tolerances.
2006-09-07 Synopsys, SMIC team on ref design flow 3.0
Synopsys Inc. and Semiconductor Manufacturing International Corp. announced that they have jointly developed and deployed reference design flow 3.0
2006-10-31 Synopsys unveils DFM tools for 45nm, beyond
Synopsys has unveiled a new family of process-aware DFM products that analyze variability effects at the custom/analog design stage for 45nm and smaller designs
2008-07-01 Synopsys gears up for 'techonomic' challenges
According to chairman and CEO of Synopsys Aart de Geus: There's a trade-off between innovation, execution and collaboration. You can execute, but if you don't collaborate with the right people, you have nothing.
2004-09-01 Synopsys CEO calls for DFM cooperation
Synopsys CEO called on the design and fab communities to develop
2005-07-15 Synopsys announces support for Oasis file transfer format
Synopsys Inc. said that its Galaxy design platform and design-for-manufacturing (DFM) tool suite support the entire Open Artwork System Interchange Standard (Oasis) file transfer format with all current production releases.
2008-03-17 Succeed at 65nm design
A true DFM-aware environment accounts for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library, continues through implementation, analysis and optimization, and ends with sign-off verification
2006-10-16 Startups take on analog design automation
Automating analog IC design has proven to be a tough challenge, but two EDA startups are promising to do just that with a new "analog synthesis" technology
2005-07-19 Speakers eye design-manufacturing link
Viable system-on-chip (SoC) business models require an integration of design and manufacturing, along with new types of businesses and alliances, according to several speakers at the Multi-Processor SoC (MPSoC) forum
2010-12-06 SMIC chooses Cadence for 65-nm reference flow
Cadence Design Systems, Inc., has just announced that SMIC has adopted Cadence Silicon Realization products for the DFM and low-power technology at the center of SMIC's 65-nanometer Reference Flow 4.1
2010-06-22 Silicon-validated library tailored for 28nm designs
GlobalFoundries rolls a silicon-validated solution to help customers accelerate time-to-volume for complex SoC designs at 28nm and beyond
2012-02-10 Samsung, Cadence partner in nanometer SoC design
The companies will collaborate on a design-for-manufacturing (DFM) infrastructure to tackle physical signoff and electrical variability optimization for 32, 28 and 20nm ICs.
2007-09-04 Qualcomm joins IMEC's 45nm design program
Qualcomm has joined IMEC's technology-aware program and will be collaborating with the research institute on design methodologies for sub-45nm scaling challenges
2005-09-23 Platform partners integrate design-for-manufacturing
IBM, Chartered Semiconductor Mfg and Samsung Electronics Co. Ltd have entered into an initial set of solutions for their cross-fab, common design-for-manufacturability (DFM) initiative. The multi-faceted effort, which includes participation by electronic design automation (EDA) and DFM tool suppliers, is expected to offer a series of rules, models and utility kits that provide new levels of predictability and control to achieve working silicon faster and yield ramp more efficiently
2004-03-26 Panelists cite shortcomings of process design kits
The process design kits (PDKs) issued by foundries to chip designers are difficult to keep current, and may place too much reliance on design rules, according to panelists at the International Symposium on Quality Electronic Design (ISQED) here March 22, 2004
2005-09-22 No scapegoats found for failed chip designs
Asked who shoulders the blame when nanometer IC designs don't work, panelists at the Custom Integrated Circuits Conference (CICC) here Tuesday evening (Sept. 20) agreed that designers, foundries, and EDA vendors all share the responsibility for ensuring success at advanced process geometries
2005-10-07 New DFM reference design flow for austriamicro's CMOS process
austriamicrosystems' business unit Full Service Foundry recently announced the availability of its DFM reference design flow for its 0.35?m high-voltage CMOS process
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