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2015-12-29 What is lacking in Design for Testability
The design part of design-for-test has been largely overlooked for far too long. In this article, we examine the hurdles and see what we can do to improve design activities for testability.
2003-09-24 Verification, test providers form outsourcing body
Six providers of services and tools for IC verification and test have banded together to form Expert Services and Tools for Semiconductors (ESTS
2007-09-03 Tips for successful structured ASIC designs
The use of structured ASIC for custom IC design is an increasingly attractive option. This article provides useful tips for structured ASIC designs
2001-11-16 The cure for test anxiety
Design for test does not have to be a painful experience. Start early, develop a test strategy and remain flexible.
2014-07-07 The cost of overlooking design-for-test
To prevent costly printed circuit board rework, it is important to have an effective DFT strategy based on a close partnership and working relationship between PCB design and test engineering
2011-06-09 Test solution automates 3D IC deployment
Imec and Cadence has released a test solution that automates 3D stacked ICs deployment
2005-01-03 Test experts ponder cost of defects
Is 100 DPPM too tough to be practical for designs in 100nm or finer processes
2004-02-20 Teseda, Agilent certify STIL link between DFT, production test
Teseda Corp. and Agilent Technologies Inc. have announced the first link that ensures transportability of Design-for-Test (DFT) data between engineering and production test platforms, wherein customers of the Teseda V500 and the Agilent 93000 SOC Series can quickly and reliably validate, debug, and apply IEEE 1450 (STIL)-based production test data generated by EDA tools.
2002-10-03 Teseda ships DFT validation system for IC testing
Teseda Corp.'s DFT-focused validation system allows engineers to rapidly validate test for prototype ICs and cut time-to-volume production
2004-10-05 System level design is here, Synopsys CTO says
System level design is happening now but it remains to be seen whether it will become EDA's next big thing
2008-03-18 Synopsys, SMIC tip 90nm reference design flow
Synopsys Inc. and SMIC have released an enhanced 90nm hierarchical, multivoltage RTL-to-GDSII reference design flow that benefits from advanced synthesis, design-for-test and DFM capabilities.
2002-05-14 SoC test reels out of control
System-level IC testing, already complicated by increasing chip capacity and the growing use of third-party intellectual property (IP), is now being threatened from another quarter.
2005-07-18 SiP modules call for right blend of tech
The SiP solution offers a seemingly limitless combination of silicon, package and component technologies that simplify overall system design
2011-01-10 Simplify automotive ASIC design with FMEA
Learn about failure modes and effects analysis (FMEA), an essential tool to examine all aspects of a product specification.
2004-02-02 Serial storage SoCs demanding to test
The storage industry this year began widespread implementation of serial-based technologies to replace parallel physical-interface standards currently used to connect a system bus to disk storage devices.
2004-06-17 SCAN90CP02 design for test features
This app note shows several SCAN90CP02 designs for test features
2004-12-01 Scan design called portal for hackers
Any chip that uses scan designand any system built around it--may be vulnerable to hackers
2008-02-01 Perform low-power manufacturing test (Part 2
Synopsys' Chris Allsup explores in this article two DFT methodologies that take advantage of recent advances in ATPG technology to automate the generation of low-power manufacturing tests.
2008-01-16 Perform low-power manufacturing test
This article by Chris Allsup of Synopsys will first examine the relationship between dynamic power consumption and test to determine why managing power is more critical today than ever before. Then, it will explore two distinct DFT methodologies that take advantage of recent advances in ATPG technology to automate the generation of low-power manufacturing tests
2004-03-12 Mentor Graphics works on China's chip design industry
Mentor Graphics Corp. has signed a memorandum of understanding (MoU) with China's Ministry of Education (MOE) to help the country boost its IC design engineering talent pool and overall industry growth
2005-06-30 Mentor Graphics scan test tool in TSMC's Reference Flow 6.0
Mentor Graphics announced that TSMC has added the TestKompress scan test tool to its Reference Flow 6.0
2005-03-08 Mentor Graphics offers TCS with design-for-test tools
Mentor Graphics Corp. announced that Tata Consultancy Services (TCS), an information technology consulting and service provider, has selected Mentor Graphics design-for-test (DFT) tools.
2004-10-08 Mentor automates test tools, adds guru to staff
Mentor Graphics Corp. has added new automated functionality to its FastScan automatic test pattern generation tool (ATPG) and its TestKompress embedded deterministic test tool
2004-10-27 Magma, Teseda provide IC implementation, test flow
Magma Design Automation Inc. and Teseda Corp. have validated the interface between Magma's IC implementation system with built-in design-for-test (DFT) and Teseda's OpenDFT WorkBench software.
2006-06-16 Low-power IC test can be trying
For designers, power management means controlling leakage power lost during standby mode and dynamic power consumption when multiple transistors switch in unison to perform desired functions
2007-05-16 Low-power IC design kit enables representative design
The Low-Power Methodology Kit from Cadence Design Systems includes a wireless "representative design" implemented using multiple supply voltage and power shutoff methods
2005-09-13 Indian researchers propose new SoC test method
With efficient test access architecture of much interest to the SoC design and test community, two researchers at an Indian technical institute have proposed a design-for-test method for digital SoC designs using a Test Access Mechanism (TAM) switch.
2012-08-09 Improve SoC yields with diagnostic and repair tools for embedded memory
Learn about embedded memory test solutions, including fault detection in very deep submicron technologies, repair at the manufacturing level, as well as diagnosis for process improvement and field repair capabilities
2013-01-24 Imec, Cadence team up for DFT solution for 3D memory
Cadence's and imec's solution includes generation of DRAM test control signals in the logic die and inclusion of the DRAM boundary scan registers test access mechanisms of the 3D test architecture
2006-04-17 IC design flow integrated
Synopsys offers its customers the Pilot Design Environment, an integrated RTL-to-GDSII design system tailored to each customer's design infrastructure
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