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2005-06-13 TSMC releases reference design flow for 65nm processes
Taiwan Semiconductor Mfg Co. Ltd has released version 6.0 of its reference flow, the sequence of EDA tools that the world's largest foundry recommends for its 65nm manufacturing processes.
2007-07-16 TSMC pulls curtains off 45nm design process
Taiwan Semiconductor Manufacturing Co. Ltd unveiled its latest and most ambitious design methodology for IC production at the challenging 45nm node
2008-04-30 TSMC IC design collaboration strategy stirs controversy
TSMC has unveiled a new and possibly controversial strategy that involves more collaboration in the early stages of the IC design process
2013-09-10 TSMC certifies Synopsis' design solution for 16nm FinFETs
Synopsys' Laker custom design solution provides users with access to a wide range of TSMC process technologies, from 180nm to 16nm
2002-04-11 TransEDA SoC verification tool combines emulation, simulation results
Designed to accelerate SoC verification, TransEDA plc's VN-Cover Emulator allows users to collect coverage data, and merge them with simulation results to measure a design's verification completeness
2003-06-05 TransEDA debuts property verification tool
TransEDA has announced a property and assertion capture and validation tool at the 2003 Design Automation Conference.
2002-09-16 Toshiba, Neolinear formulate new methodology for Soc design
Toshiba and Neolinear teams up to implement a new AMS design methodology that enables significant analog design reuse
2004-12-21 Toshiba supports Cadence RTL compiler for ASIC design
Cadence Design Systems Inc. announced that Toshiba America Electronic Components Inc. (TAEC) has introduced a design kit to support its custom System-on-Chip (SoC) and ASIC customers using Cadence Encounter RTL compiler synthesis
2004-11-22 Toshiba adopts Mentor ADVance MS tool in LSI designs
Mentor Graphics Corp. revealed that Toshiba Corp. has adopted its analog/mixed-signal HDL language, Verilog-AMS, for the design and verification of complex analog and mixed-signal LSI (large scale integration) designs
2008-06-23 Tool with object-oriented GUI eases RF design
Keithley Instruments Inc. has released Version 2.0 of its SignalMeister waveform creation software.
2005-02-01 Tool vendors dispute report of downturn in ESL
Did the emerging ESL tools market take a
2003-05-15 Tool vendor @HDL licenses solvers from IBM
@HDL has licensed formal verification technology from IBM Corp. and plans to incorporate the technology into its current product line in the coming months.
2007-03-28 Tool taps clock gating for IC power optimization
Claiming breakthrough technology in IC power optimization, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code.
2007-05-31 Tool tackles power integrity issues in ICs, packages, boards
Aiming to deliver a comprehensive solution for tackling noise and power at the chip, I/O and PCB design levels, Apache Design Solutions announced its Sentinel product line
2008-09-04 Tool suite upgrade touts faster fault detection
LDRA, the leading provider of automated software verification, source code analysis, and test tools, has launched the LDRA tool suite v7.7
2009-06-22 Tool suite speeds up multiprocessor apps design
Multiprocessor design company 3L Ltd has introduced the latest version of its Diamond multiprocessor tool suite.
2006-07-01 Tool suite handles design complexity
Altera Corp. recently launched its Quartus 6.0 tool suite, which includes a timing analyzer that's said to pave the way for next-generation 65nm FPGAs
2005-10-19 Tool suite 'lays foundation' for extending TCAD to DFM
Synopsys introduced early this week a new TCAD tool suite that integrates features of former TMA and ISE products as well as adding new capabilities that enable TCAD to be used in the manufacturing space
2008-01-24 Tool speeds up design of optoelectronic devices
Acceleware and Synopsys have developed a hardware solution that enables up to 20x faster electromagnetic simulation of optoelectronic devices such as CMOS image sensors.
2009-05-07 Tool simplifies on-chip interconnect design
EDA vendor Sonics Inc. has rolled out a new tool to ease the job of building on-chip interconnects using the ARM Amba bus
2003-12-10 Tool set eyes process test-chip design
Silicon Canvas Inc. will release a platform for process test-chip development that the company calls the first commercial product of its kind. The Laker T1 platform is designed to help foundries and integrated device manufacturers create test chips to verify, optimize and calibrate new silicon processes.
2007-11-16 Tool rids wireless sensor nets of battery
No wires and no batteries; now there's a combination. It's the promise of a company at this year's ISA Expo with a battery-free solution for ultralow-power wireless sensor and control networks based on the IEEE 802.15.4 standard.
2006-11-01 Tool reduces need for immersion at 45nm
Invarium Inc. offers patterning-synthesis software promising, among other things, to limit the number of advanced layers that will require immersion at 45nm. This will allow customers to get more mileage out of existing lithography equipment.
2003-12-23 Tool promises parallelizing synthesis
Touting a new approach to parallelizing, high-level synthesis, the Center for Embedded Computer Systems at the University of California at Irvine has released its Spark synthesis tool to engineers. Available as a free download, Spark takes C-language input and produces register-transfer-level VHDL code
2004-03-17 Tool pinpoints false paths, steers designers away
FishTail Design Automation is targeting what sounds like a small niche, but the company says the potential benefits of its technology are huge
2006-11-16 Tool makes ADI chip evaluation easier
Analog Devices Inc. has developed a Web-based evaluation tool for direct digital synthesis (DDS) ICs sold by the company
2006-09-20 Tool limits need for immersion lithography at 45nm
Invarium will roll out new patterning-synthesis software this week, promising, among other things, to limit the number of advanced layers that will require immersion at 45nm.
2005-03-17 Tool improves design practices
Cypress MicroSystems announced a new development tool designed for Cypress' PSoC mixed-signal arrays that claims to dramatically improve mixed-signal design practices.
2006-02-23 Tool generates verification plans from design specs
Severity One is starting to sell Relay, a tool that produces reusable, coverage-driven verification plans from textual specifications or user input through a graphical user interface
2006-07-28 Tool enables designers to generate fast virtual prototypes
ARM announced the ARM RealView System Generator tool, which promises to enable platform providers to rapidly generate, by themselves, instruction-accurate virtual prototypes
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