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2014-07-07 The cost of overlooking design-for-test
To prevent costly printed circuit board rework, it is important to have an effective DFT strategy based on a close partnership and working relationship between PCB design and test engineering.
2004-06-17 SCAN90CP02 design for test features
This app note shows several SCAN90CP02 designs for test features.
2005-03-08 Mentor Graphics offers TCS with design-for-test tools
Mentor Graphics Corp. announced that Tata Consultancy Services (TCS), an information technology consulting and service provider, has selected Mentor Graphics design-for-test (DFT) tools.
2003-08-01 Design-for-test moves up to RT level
SynTest Technologies propelled its entire DFT flow up to the RTL with DFT-Pro Plus, thereby lessening the likelihood of errors.
2003-07-22 Design-for-test has multiple dimensions, experts say
Papers presented at the production test session at Semicon West surveyed the increasing problems that technology integration is causing for the test world.
2005-10-20 Design-for-test analyzer validates boundary-scan
A product called DFT Analyzer from ASSET InterTech promises to reduce manufacturing and test costs when it debuts early next year.
1999-10-01 Design for Test considerations for ATPG
This article describes techniques for designing ICs to facilitate ATPG, and explains the importance of compact test vector generation in the overall design flow.
2004-02-20 Teseda, Agilent certify STIL link between DFT, production test
Teseda Corp. and Agilent Technologies Inc. have announced the first link that ensures transportability of Design-for-Test (DFT) data between engineering and production test platforms, wherein customers of the Teseda V500 and the Agilent 93000 SOC Series can quickly and reliably validate, debug, and apply IEEE 1450 (STIL)-based production test data generated by EDA tools.
2002-10-03 Teseda ships DFT validation system for IC testing
Teseda Corp.'s DFT-focused validation system allows engineers to rapidly validate test for prototype ICs and cut time-to-volume production.
2003-09-15 SynTest appoints Logicad as distributor in India
SynTest Technologies Inc., a provider of design-for-test (DFT) technology, has signed Logicad Technologies as its distribution partner for India.
2008-03-18 Synopsys, SMIC tip 90nm reference design flow
Synopsys Inc. and SMIC have released an enhanced 90nm hierarchical, multivoltage RTL-to-GDSII reference design flow that benefits from advanced synthesis, design-for-test and DFM capabilities.
2004-05-25 STATS expands turnkey solutions with DFT capabilities
STATS has expanded its integrated turnkey solutions with DFT capabilities that will assist customers in improving testability and throughput of their devices.
2003-09-15 Silicon 'debug' product serves Synopsys DFT users
Claiming to dramatically speed test vector debug time for users of Synopsys' DFT products, Intellitech Corp. has announced the Nebula silicon debugger.
2010-11-03 Ricoh licenses DeFacTo's DFT solution
Ricoh Company Ltd announced the licensing of the HiDFT-Signoff Design-for-Test solution of DeFacTo Technologies SA.
2001-06-01 Practical DFT leads to highly testable ASICs
Combine classic design-for-test methodologies, such as scan and BIST, with practical DFT, to clear the path to a highly testable design
2008-02-01 Perform low-power manufacturing test (Part 2)
Synopsys' Chris Allsup explores in this article two DFT methodologies that take advantage of recent advances in ATPG technology to automate the generation of low-power manufacturing tests.
2008-01-16 Perform low-power manufacturing test
This article by Chris Allsup of Synopsys will first examine the relationship between dynamic power consumption and test to determine why managing power is more critical today than ever before. Then, it will explore two distinct DFT methodologies that take advantage of recent advances in ATPG technology to automate the generation of low-power manufacturing tests.
2013-10-03 Online quoting service drastically cuts MPW quote time
eSilicon's automated, instant, online quoting service for MPW Shuttle Services takes only around 15 minutes, a vast improvement from the usual process that takes 40 hours.
2004-10-27 Magma, Teseda provide IC implementation, test flow
Magma Design Automation Inc. and Teseda Corp. have validated the interface between Magma's IC implementation system with built-in design-for-test (DFT) and Teseda's OpenDFT WorkBench software.
2002-07-19 LogicVision establishes engineering support division
LogicVision Inc. has formed an Engineering Support and Services Division to provide engineering and consulting services for chip, board and system level design-for-test.
2009-10-08 Improve yield with layout-aware DFT
This article discusses the approach to figure out those areas from the layout that has higher probability of physical malfunctioning. The design for test (DFT) tools can then generate top-up test patterns for these areas.
2013-01-24 Imec, Cadence team up for DFT solution for 3D memory
Cadence's and imec's solution includes generation of DRAM test control signals in the logic die and inclusion of the DRAM boundary scan registers test access mechanisms of the 3D test architecture.
2013-09-13 How to avoid PCB engineering change orders
Prevent engineering change orders in printed circuit board designs by paying attention to seven key areas where problems are likely to occur.
2000-09-01 Formal verification by equivalence checking in deep sub-micron designs
Equivalence verification tools compare the logical behavior of two circuits while ensuring a consistent design flow. They aim to combine structural checking with handling of multi-million gate designs in a small memory footprint.
2004-06-01 EDA startup preps tools for RTL closure
Blue Pearl Software said its upcoming technology will identify and fix functional and DFT errors in RTL code, locate false paths and automatically generate timing constraints for synthesis.
2005-11-04 Diagnostic tool from Mentor enhances semiconductor yield
Mentor Graphics Corp.'s YieldAssist diagnostic tool to enhance semiconductor yield and expand the DFT product portfolio and platform.
2006-10-16 DFT rule checkers glue design together
Advances in DFT rule checking will likely continue as more designs depend on increasingly complex testing protocols.
1999-01-01 Designing embedded memories using 4G compilers
Embedded memories gain over standalone memories in terms of power consumption, performance, flexibility of use, and test and diagnostics. Use fourth generation compilers to embed memories on a chip to realize the quality and reliability of standalone ones.
2000-05-01 Design for Testability guidelines in a combined x-ray, in-circuit environment
The technique allows engineers to build assurances in testing complex PCBs during the design phase. By enabling shorter development cycles, DFT offers optimum production speeds resulting in faster time-to-market.
2013-01-02 Apply formal methods to power-aware verification
Read about an apps approach for implementing formal methods to power-aware verification.
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