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2010-03-02	SPIE Litho wraps with delays, double-patterning The themes of this year's SPIE Advanced Lithography event were clear: D and D—delays and double-patterning. Indeed, EUV is delayed. So is maskless. And nanoimprint is still stuck in R&D.
2013-06-06	Parasitic extraction in the double-patterning age Determining the impact of double-patterning on electrical sign-off can be better achieved by understanding how PEX tools have evolved to handle this challenge.
2009-12-15	Nikon eyes litho rebound with double-patterning Nikon Corp. is looking to regain share, especially in the upcoming double-patterning era, according to an analyst.
2008-07-22	EUV delays drive shift to double-patterning With the probable delays for EUV lithography, ASML, Canon and Nikon are racing each other to capitalize on the shift towards double-patterning technology at the 32nm node and beyond.
2009-03-02	Panelists skeptical on next-gen litho Experts debated and sparred over the future of patterning during a panel discussion at the SPIE Advanced Lithography conference.
2009-02-25	Intel: EUV litho roadblocks ahead A top technologist at Intel Corp. warned that a lack of mask inspection gear for extreme ultraviolet (EUV) lithography is threatening the process' future viability in the market.
2009-06-23	Intel scales down 193nm litho to 15nm Intel claims that it has pushed 193nm immersion lithography down to 15nm—at least in the lab.
2011-07-20	IC compiler configuration touted 20nm-ready Synopsys has launched the IC Compiler-Advanced Geometry, a configuration of its IC Compiler physical design product which targets design support for double-patterning technology.
2011-09-01	GlobalFoundries tests 20nm chip GlobalFoundries has manufactured a 20nm test chip utilizing design tools from other design companies such as Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys.
2010-02-26	EUV delay forces tool makers to check other options EUV lithography is delayed again and is now targeted for chip production at the 16nm half-pitch node, leaving the industry to face the dreaded double-patterning or some variation of the technology.
2013-01-30	Cadence unveils Virtuoso Advanced Node for 20nm Cadence Design Systems has taken the wraps off Virtuoso Advanced Node, which enables the development of complex mixed-signal chips.
2010-01-08	Buzz: TSMC buys Nikon 193nm litho scanner In a surprise move, TSMC has procured a new 193nm immersion lithography scanner from rival Nikon Corp., according to sources.
2013-07-19	Address DRC debug issues in 20nm custom designs Know the new debugging solutions that can help custom designers quickly and effectively achieve DRC closure on their advanced node designs.
2012-06-13	20nm is a different playing field, says exec According to Synopsys Inc.'s Saleem Haider, the requirement for lithography double patterning on many layers makes moving to the 20nm node a major undertaking that will require customers to invest in new design tool sets.
2015-06-23	What's inside 1Xnm planar NAND? Double patterning has become mandatory for making the 16nm node NAND flash and the memory makers use a self-aligned double patterning for the active, control gate, floating gate and bitline patterning.
2012-05-17	Tool eases migration to 28nm, 20nm Sagantec's nmigrate layout migration and optimization tool can migrate and DRC-correct cell layout and make sure the layout adheres to all advanced design rules, including coloring for double patterning.
2014-03-20	Samsung announces prod'n of 20nm-based 4Gb DDR3 memory A key element of the latest design and manufacturing technology by Samsung is a modified double patterning and atomic layer deposition that allows for continued scaling.
2008-02-06	Will EUV litho ever cross over from R&D to production? The procurement of an R&D EUV lithography tool from Nikon has reportedly been put off by Intel, raising more questions about the viability of EUV for mass chip production.
2014-12-18	What's hot at IEDM 2014? The 2014 International Electron Devices Meeting proved that Moore's Law is still alive. The event was a victory lap for Intel, which gave more details on the 14nm finFET process.
2009-04-09	Unlock Micron's 50nm DRAM technology With their latest 50nm process technology, Micron Technology Inc. seems to have struck the right balance between investment in new technologies and conservative design decisions.
2010-07-20	Uncertainty marks future of advanced lithography Industry players present in Semicon West's session on advanced lithography sparked arguments on what the future holds as complexities and costs increase.
2008-11-27	UMC pushes high-k process for 45nm Foundry United Microelectronics Corp. has validated its high-k metal gate process with a test SRAM design run at the 45nm node.
2008-04-29	TSMC throws hat in 32nm high-k ring TSMC has outlined details of its 32nm road map, giving an impression it may be playing catch-up with its foundry rivals, particularly in the emerging arena of high-k materials and metal gates.
2008-06-12	TSMC targets to unify 32nm design flow Facing the 32nm challenge, Taiwan Semiconductor Manufacturing Co. Ltd is putting the pedal to the metal with a new design-for-manufacturing scheme.
2010-03-01	TSMC takes on 40nm yields, high-k, litho issues At the TSMC Japan Executive Forum in Yokohama, Shang-Yi Chiang, senior VP of R&D at TSMC, addressed several issues about the silicon foundry giant.
2014-10-07	TSMC takes lead over Samsung in FinFET race TSMC's 16nm pilot line is gaining incremental confidence among prospective customers, leaving behind Samsung, whose foundry has experienced a setback with its 14nm FinFET project.
2010-04-15	TSMC skips 22nm, leaps to 20nm half-node Taiwan Semiconductor Manufacturing Co. Ltd announced plans to skip the 22nm "full node" after the 28nm node and move directly to the 20nm "half node."
2012-04-20	TSMC shifts from multiple to single-only process at 20nm Shang-yi Chiang, EVP at TSMC, said the firm might also offer an 18nm or 16nm process node after 20nm if lithography technology is not available to make 14-nm devices cost effectively.
2012-10-11	TSMC releases 20nm, CoWoS design reference The silicon-validated CoWoS Reference Flow enables multi-die integration to support high bandwidth, low power and can achieve fast time-to-market for 3D IC designs.
2015-09-21	TSMC heats up 10nm engine, preps 16nm for 2017 TSMC has gotten off to a slow start with its 16nm FinFET process and has also announced plans for specialty RRAM and MRAM memories that would act as alternatives to embedded flash.