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2013-09-06 Static vs dynamic analysis for code devt (Part 2)
This second instalment focuses on dynamic code analysis.
2013-09-04 Static vs dynamic analysis for code devt (Part 1)
Consider the strengths and weaknesses of static and dynamic code analysis in the development of secure C or C++ code.
2008-05-01 Eliminate bugs with static analysis
Static source code analysis tools have evolved from simple syntax checkers to powerful tools for identifying flaws in the complex interactions of large code bases
2007-05-16 Analyze source code for Net app flaws
Automated source code analyzers are good at locating anomalies. They can also be used with little or no impact on build times and are easily integrated with the regular software development environment
2009-02-16 Uncovering static analysis pitfalls
Perhaps the most surprising thing about static analysis is not that it can detect memory leaks, buffer overflows, or incorrect pointer assignments at compile time, but rather that users of static analysis will often fail to fix such detected defects
2013-12-11 Securing open source web apps with static analysis
Find out how static analysis can be used to find and eliminate coding errors
2003-09-01 Predictive analysis for low-power IA designs
Predictive analysis techniques incorporates low-power design techniques and ensures adherence to new design methodologies
2004-12-01 Memory analysis tools get first revision
PowerEscape launched its first tools in January and is now releasing its first major revision of those products, touting enhanced features and a smoother methodology.
2009-03-31 Finding defects in safety-critical code
The methods that safety-critical developers use are undeniably effective at reducing risk, so there are lessons to be learned for developers who do not write safety-critical code. Two techniques stand out as being most responsible: advanced static analysis and rigorous testing
2009-02-11 Effectively implement a static analysis tool
The beginning and end of effective process for static analysis could be summed up as "inspect every defect and fix all defects
2005-09-01 DSA board on PCI bus from NI with 118dB dynamic range
National Instruments unveiled the PCI-4461 module, which is a 24bit data acquisition and generation module that is said to mark the highest-performance dynamic signal acquisition board on the PCI bus with a 118dB dynamic range
2005-05-09 Atrenta expands RTL analysis and verification
Claiming new capabilities for IC design, Atrenta rolled out "predictive development" tools for RTL analysis and assertion-based verification last week
2004-05-07 ACAD analysis tool achieves SPICE-level accuracy
ACAD has disclosed that its new FineSim hybrid simulation analysis tool can achieve SPICE-level accuracy
2014-11-25 Improve software through memory layout optimisation
In this second instalment, we will provide tips on various memory layout optimisation techniques that can be used to improve embedded system performance.
2003-12-01 Startup tackles system architecture
VisualSim, a toolset for performance analysis and architectural exploration using the Ptolemy simulation kernel, offers to combine DSP, analog, protocols and digital architecture in a single simulation
2011-10-10 Pros and cons of different high speed digital tests
Here's a discussion on the relative merits and demerits of high speed digital test approaches and dynamic protocol reconfiguration
2015-03-06 Multi-core concurrency: Opportunities and hurdles
In this article, we provide a basic outline of the principles of concurrency, a fundamental mechanism by which multi-core systems manage and coordinate multiple tasks in parallel to achieve higher performance.
2014-08-25 Matlab software expands Keysight oscilloscope features
Keysight Technologies revealed that the frequency domain analysis option for some of its oscilloscopes allows users to extend the device's analysis capabilities
2016-03-24 Explore model-based testing for production hardware
Here is a look at Time Partition Testing, a model-based testing technique, which is based on hybrid, hierarchical, parallel running automatons with continuous behaviour.
2006-10-16 Achieve low-power design success at 65nm
Tom Chau and Cheng Shi compile tips for designers to ensure success for advanced low-power designs at 90nm and 65nm.
2011-05-04 Design software supports UVM
SpringSoft has announced complete support for UVM with its Verdi Automated Debug System that enables UVM code and enhanced transaction-level analysis to ease debug of SystemVerilog testbenches
2007-03-28 Tool taps clock gating for IC power optimization
Claiming breakthrough technology in IC power optimization, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code
2008-09-04 Tool suite upgrade touts faster fault detection
LDRA, the leading provider of automated software verification, source code analysis, and test tools, has launched the LDRA tool suite v7.7
2004-08-12 Synthesis suite targets unconventional designs
FTL's Merlin is a tool suite that includes behavioral synthesis from VHDL or SystemVerilog; analog synthesis from VHDL-AMS or Verilog-AMS; and analysis and simulation
2003-10-07 Startup tackles system architecture
Mirabilis Design Inc. is quietly shipping a toolset for performance analysis and architectural exploration
2015-06-05 Energy sector begins hunt for cognitive computer
Dynamic Risk announce the Cognitive Computing Challenge, a $200,000 incentive prize for developing real-time cognitive software that combines data mining and pattern recognition techniques
2013-03-25 Analyse RTL clock gating to cut processor power
The focus on clock gating and the fast turnaround of RTL analysis allow measurable power reductions for typical applications of X86 AMD core
2010-05-28 Timing analyzer speeds up multicore designs
XMOS has released the XMOS Timing Analyzer (XTA) that accelerates the design of embedded applications using its family of XCore processor arrays.
2007-02-05 Xilinx upgrades free ISE Webpack design suite
Xilinx has announced the immediate availability of the ISE WebPACK 9.1i release, the latest version of the company's free downloadable programmable logic design suite.
2007-01-18 Xilinx ISE upgrade shortens FPGA design cycles
Xilinx' ISE 9.1i design suite is optimized to meet today's leading design challenges: timing closure, productivity and power.
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