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2004-04-06 Synopsys forum updates SystemVerilog support
The message at the Synopsys EDA Interoperability Developer's Forum, convening Thursday (April 1, 2004), is clear; SystemVerilog support is growing
2004-03-31 Synopsys CEO defends MoSys acquisition
Responding to user questions on a variety of topics, Aart de Geus, Synopsys CEO, defended his company's proposed acquisition of MoSys in a new E-Mail Synopsys User's Group (ESNUG) mailing.
2004-04-22 Canceled Synopsys-MoSys deal seen headed to court
Synopsys Inc.'s abrupt termination of its merger agreement with memory IP vendor Monolithic System Technology Inc. (MoSys) will likely prompt MoSys to seek a shotgun wedding through a lawsuit, according industry analysts
2005-02-15 Users laud C design in DAC 'trip report'
Engineers are warming to C language design tools, according to reviews in the Design Automation Conference (DAC) &quote;trip report&quote; released Friday (Feb. 11) by industry gadfly John Cooley.
2004-03-15 User lauds unreleased Design Compiler version
A special pre-release version of Synopsys' Design Compiler synthesis tool is demonstrating huge improvements in runtime and memory capacity, according to an engineer who reviewed the tool for the E-Mail Synopsys Users Group.
2004-04-06 Mentor FPGA synthesis users speak out
Over 50 users of Mentor Graphics FPGA synthesis tools shared their stories in the latest edition of the E-Mail Synopsys Users Group (ESNUG), adding credibility to a report that Mentor has increased its market share.
2004-03-15 Engineer offers free obfuscator, layout scanner
Inspired by a user request in the E-Mail Synopsys Users Group (ESNUG), an engineer working in Singapore developed a Verilog source-code obfuscator, a GDSII layout viewer, and a layout scanner that calculates wire length.
2003-09-12 EDA users call for 64-bit Opteron support
A number of EDA users would like to run 64-bit apps on AMD Opteron servers, but are frustrated by the lack of EDA vendor support.
2004-01-05 EDA startup offers graphical Verilog tool
Aiming to simplify HDL code development and documentation, Orion Consulting Inc. has rolled out Visual RTL.
2003-12-19 Designers stand up for gate-level simulation
In theory, static timing analysis and formal verification should render gate-level simulation unnecessary. But in reality, it's unavoidable, according to a number of engineers who contributed postings to the latest E-Mail Synopsys Users Group (ESNUG) bulletin.
2003-04-04 Chip designers debate asynchronous resets
Chip designers are divided when it comes to choosing synchronous or asynchronous resets, according to postings in the latest E-Mail Synopsys Users Group 409 bulletin.
2004-09-20 Cadence users mixed on tools and services, survey says
Cadence users ranked First Encounter as its best tool and Assura as its worst and said they like local but not hot-line support, according to a user study presented Sept. 14 at the Cadence Users Group meeting.
2004-06-01 Behavioral synthesis crossroad
Ten years after its market entry as the next generation in synthesis, Synopsys' Behavioral Compiler is dead. Can somebody else breathe new life into behavioral synthesis
2002-10-01 'Religious' wars abound
Should resets be synchronous or asynchronous? Should synthesis handle buffer insertion? Should OpenVera assertions be added to System Verilog? All these questions have provoked controversies in recent weeks, the first two in E-Mail Synopsys Users' Group (ESNUG) postings and at our EEdesign site.
2004-03-17 Tool pinpoints false paths, steers designers away
FishTail Design Automation is targeting what sounds like a small niche, but the company says the potential benefits of its technology are huge.
2005-10-27 Survey finds verification tool use largely unchanged from 2004
The 2005
2003-12-08 Mentor get "physical" with FPGA synthesis
Mentor Graphics will roll out what it calls the first "integrated" RTL and physical FPGA synthesis solution.
2006-02-01 Language standards from IEEE open choices
Once seen as competitors, SystemC and SystemVerilog languages appear to be settling into largely complementary niches.
2004-03-08 EDA CEOs field provocative questions
In a broad-ranging panel discussion at the Design and Verification Conference (DVCon), moderator John Cooley asked EDA CEOs a variety of provocative questions - and received some spirited responses.
2002-10-09 Apache's Tomahawk tool analyzes power, IR drop
EDA startup Apache Design Solutions Inc. has released the Tomahawk-S static analysis tool that looks at power, IR drop, and electromigration.
2005-08-01 Tool buffs up regression testing
AVS provides a browser interface that serves as a control panel for the verification process where jobs can be launched, suspended or terminated.
2007-06-18 The intricate dance of cutting power consumption
Key players in the industry are collaborating to deliver low-power solutions that bring more automated EDA tools, smarter IP, standard formats and more power-stingy processes together into true end-to-end solutions. EDA and IP companies have worked within the Accellera standards organization to develop the Unified Power Format (UPF).
2006-10-16 Open-source tools ease C++ verification
Two engineers published a book on IC verification with C++ and launched a website with free open-source tools that can help IC verification teams.
2004-11-04 MatrixOne upgrades Synchronicity suite
MatrixOne released the first revision of Synchronity technology since it acquired Synchronicity in June 2004.
2007-03-23 Hope fades for IC power standards union
The hoped-for-convergence between two rival IC low-power specifications will not likely take place anytime soon.
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