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total search20 articles
2008-02-18 Why we need a new analog design flow
Analog-mixed signal designers need a first-time right design methodology now. Why is this familiar cry more urgent and probably truest this time?
2016-02-11 X-FAB Award calls for new design concepts in semiconductors
X-FAB to look into integration of advanced design and functionality, awarding the winner with a free prototyping run to validate their ideas in the best-suited technology
2010-05-18 Wipro taps Mentor tools to reduce design time
Mentor Graphics Corp. and Wipro Technologies are partnering to continue to enable time-to-market and first-time right solutions to their global product engineering customers
2005-07-19 Speakers eye design-manufacturing link
Viable system-on-chip (SoC) business models require an integration of design and manufacturing, along with new types of businesses and alliances, according to several speakers at the Multi-Processor SoC (MPSoC) forum
2005-06-10 Seiko Epson licenses Sarnoff's design IP
Seiko Epson Corp.'s semiconductor unit said it will license design know-how from Sarnoff Europe for use in its LCD driver ICs
2013-03-15 Issues in using 3rd party IP in ASIC/SoC design
Know some of the common challenges in integrating and using 3rd party IPs in today's high-end ASIC/SoCs.
2005-09-27 India gearing for outsourced ESL design
India's software skill base, growing hardware design skills and the increasing software content in electronics is making the country a likely source of Electronic System Level (ESL) design
2010-03-16 IMEC, Altos join hands on design, prototyping service
IMEC and Altos Design Automation Inc. are partnering to set up a library re-characterization service based on Altos' ultrafast characterization tools
2011-01-17 Globalfoundries launches 28nm signoff-ready digital design flows
Globalfoundries announced that it has 28nm silicon-validated signoff-ready digital design flows to help chip designers deliver the next generation of power-sensitive mobile and consumer electronic devices
2005-04-18 DATE minds offer an array of fixes for SoC design
Designing high-performance SoCs needs a breakthrough from system-level design through manufacturing, according to DATE
2005-03-01 RF ICs: Moore's Law on steroids
After a long period of dormancy, Moore's Law is taking hold of the wireless chip market.
2006-10-18 India's Wipro now offers post-GDS services
Wipro, an Indian technology service company, has extended its portfolio of IC design services to include post-GDS services to both fabless semiconductor and IDMs
2006-06-22 Comit expands adoption of Cadence tester
Cadence announced that Comit Systems has standardized its automatic test pattern generation flow on Cadence Encounter Test.
2005-08-30 Oki implements Sarnoff's on-chip ESD protection in high-voltage ICs
Oki Electric Ind. Co. Ltd has produced ICs in 0.5um/43V, 0.35um/16.5V and 0.25um/25V process technologies using TakeCharge design technology from Sarnoff Europe of Gistel, Belgium
2005-03-10 Cadence teams up with austriamicrosystems on analog designs
Cadence Design Systems Inc. has signed a strategic alliance with austriamicrosystems targeting analog IC design
2004-05-14 Philips claims new 90nm chip is 'right-first-time'
Philips Semiconductors has achieved what it claims is right-first-time silicon at its 90nm CMOS production lines in France and Taiwan.
2008-05-13 NXP taps Mentor Graphics' DFT tools
Mentor Graphics's DFT products will be used by NXP Semiconductors to improve the quality and time-to-market of NXP's solutions.
2013-02-14 Is the demise of high-speed I/O near?
High-speed serial interfaces featuring equalisation may be the norm in the future, and high levels of SoC integration may no longer be the best solution.
2005-01-04 austriamicro's Full Service Foundry introduces digital libraries
austriamicro's Full Service Foundry now offers digital libraries including standard cells, I/Os and memory compilers free of charge to its customers.
2005-01-04 Addressing foundry SoC challenges associated with advanced technologies
As process technologies continue to shrink to 90nm and below, new opportunities are presented to designers that allow them to combine the functions of entire systems onto a single piece of silicon.
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