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flip chip What is flip chip? Search results

What is flip chip?
A type of semiconductor mounting technique that does not require any wire bonds. The final wafer processing step deposits solder bumps on the chip pads, which are used to connect directly to the associated external circuitry.
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2004-01-22 STATS offers FCLGA package for wireless apps
ST Assembly Test Services Ltd has qualified an environment-friendly version of its Flip-Chip Land Grid Array (FCLGA) package.
2008-10-01 Stacked microprocessor system promises better performance
Take a different approach to chill. A group of researchers just did, resulting in what may be the most efficient heat dissipation possible for stacked microprocessors.
2005-06-09 ST Micro balances line capacitance, attenuation in new chips
The two new low-capacitance EMI-filter and electrostatic-discharge protection chips from STMicroelectronics are designed to suppress EMI/RFI noise in sensitive, high-volume equipment
2001-04-15 Solder flux jetting technology
Advances in jetting technology improve film thicknesses and provide excellent edge definition in selective flux applications.
2002-01-23 Shenzhen Jinghua rolls out COG LCD panels
Shenzhen Jinghua Displays Co. Ltd has started marketing chip-on-glass (COG) LCD panels
2001-04-15 SERA tin evaluation for surface finish
Technical, economic, and environmental factors are providing the impetus to find hot air solder level (HASL) alternatives for solder finishes. SERA tin evaluation provides insights into the performance of these finishes.
2002-12-24 Semiconductor packaging market to experience growth in '03
The worldwide semiconductor packaging and assembly segment is poised for growth in 2003, according to Dataquest Inc., a unit of Gartner Inc.
2005-07-19 Resistor eases visual inspection
A new line of partial wrap termination resistors from International Mfg Services provides an exposed solder fillet that is designed to facilitate visual inspection of the flip-chip's termination joint
2008-10-01 Reap the rewards of package-aware design
Chip designers must consider package routability, power delivery and I/O behavior during the initial I/O planning process. To do so, they should combine package-aware I/O planning with automated floor-plan synthesis, which can be very cost-effective for the chip floor plan and the package layout
2010-09-15 RCP technology manufactured in 300mm format
Nepes to manufacture Freescale technology that replaces deployed ball grid array packaging
2007-11-28 Rambus shows alternative way to terabyte memory
Rambus has developed technologies that could enable links to memory chips delivering up to a terabyte per second and could provide a lower-cost alternative to 3D chip stacking
2008-01-04 Ralink tips low power, 'smallest' 802.11n chips
Ralink has released new 802.11n single chips, the RT3080 that enables Wi-Fi in handheld/mobile devices and the RT3070, claimed to be the smallest 802.11n USB single chip
2005-07-08 Quarter-brick IBCs extend to 450W
Georgia Institute of Technology researchers have developed a chip-cooling process that they hope will replace the bulky, bolt-on metal towers used with microprocessors like the G5
2004-03-16 Precision jetting allows closer component placement
One of the limitations on the close placement of components has been the space requirements for underfilling flip-chips, BGAs, and CSPs; and Asymtek's new developed solution makes it unnecessary to insert the needle between components
2009-02-19 Power converter harnesses green energy
Freescale Semiconductor Inc. has developed an integrated mixed-signal chip that can convert the output from a single solar cell into a usable power source
2011-08-29 Placement system touts high-speed die bonding
Single machine solution eases IC manufacturing with die bonding speeds at 3,500cph per head at 25?m.
2004-01-27 Parama IC reduces equipment, network costs
Parama Networks has introduced a system level solution for the design of next-gen SONET/SDH transport equipment.
2002-11-25 Optonics devices chosen to test Motorola devices
Motorola Inc. has adopted Optonics Inc.'s EmiScope-I diagnostic solution for node level timing measurement of its advanced devices.
2008-01-10 New packaging tech integrates cooling, power generation
Nextreme has integrated cooling and power generation into the copper pillar bumping process used in high-volume electronic packaging.
2005-11-29 New LED chips from SDK
Showa Denko K.K. launched gallium-nitride-based near ultraviolet and green LED chips for use in general white lighting and backlighting of large LCD screens.
2004-10-07 NEC reorganizes semiconductor assembly, testing operations
NEC Electronics Corp. has launched NEC Semicon Package Solutions Ltd, a back-end production company specializing in assembly and testing.
2004-10-18 LSI Logic takes aim at PCI Express
Targeted to the needs of PCI Express developers, LSI Logic announces a new family in its RapidChip structured-ASIC line.
2002-10-24 LSI Logic extends reach of wirebond packaging
LSI Logic Corp. has developed a form of wirebond packaging that places bonding pads directly on top of a chip's active I/O circuitry
2004-07-19 LCD protection device replaces 50 discrete devices
The Integrated Products Group of Microsemi said its new LCD protection device protects ten lines and can eliminate up to 50 discrete components.
2005-02-24 Kyocera America assembly division gets DSCC certification
Kyocera America Inc. has received DSCC (Defense Supply Center, Columbus) level Q transitional certification for assembly and test, per MIL-PRF-38535, FSC 5962 allowing Kyocera America to perform assembly and test services for defense applications.
2002-11-11 K&S opens alternatives for non-core business units
Kulicke & Soffa Ind. Inc. has announced that it is exploring options for some of its non-core business units.
2004-05-17 Jetting permits closer component placement
Jetting sharply differs from conventional needle dispensing that has been used to underfill flip-chips, BGAs, CSPs and to dispense fluids for die attach and other apps
2005-08-29 Infineon samples its all-owned DDR2 FB-DIMMs
Infineon announced that it is sampling the industry's only DDR2 Fully Buffered Dual-In-line Memory Modules with all key components designed and manufactured by a single DRAM supplier.
2005-02-17 Infineon replaces IC card wirebonding with FCOS
Chip-maker Infineon Technologies AG will be replacing its wirebonding process technology used in chip card manufacturing with flip chip-on-substrate (FCOS), which eliminates the use of wires and synthetic resin encapsulation.
2007-10-18 Industrial affiliation program tackles 32nm IC packaging
Two research centers are inviting industry partners to participate in an advanced research program on next-generation flip-chip and substrate technologies.
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