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2005-02-11 Toshiba unveils high-density DRAM with floating-body cells
Toshiba Corp. has developed 128Mb silicon-on-insulator (SOI) DRAM with floating-body cells that the chip maker claims will help usher in embedded DRAM chips on SOI wafers.
2005-09-28 Renesas reports floating-body SOI RAM
Renesas Technology said that it has developed a capacitor-less "floating-body" twin-transistor RAM (TTRAM), that would enable faster, more power-efficient embedded memory for SoC devices
2005-09-28 Renesas reports floating-body SOI RAM
Renesas Technology Corp. has developed a capacitor-less "floating-body" twin-transistor RAM (TTRAM) that would enable faster, more power-efficient embedded memory for system-on-chip (SoC) devices
2008-08-18 Memory rests hope on floating-body cells
Intel Corp. revisited its research on floating-body cells (FBCs) for advanced cache designs in microprocessors during the 2008 Symposium on VLSI technology in Hawaii.
2010-06-21 Intel details floating-body R&D progress
Intel Corp. has delivered an update on its ongoing research on floating-body cells for advanced cache designs in microprocessors at the 2010 Symposium on VLSI Circuits.
2007-08-15 Hynix licenses floating-body tech for future DRAM
Hynix has licensed the floating-body single-transistor memory technology from Innovative Silicon for use in future generations of DRAM chips.
2003-08-06 Toshiba memory cell technology eyes DRAM apps
Toshiba has developed what it claims to be the world's first memory cell technology for embedded DRAM system LSIs on SOI wafers.
2005-12-14 Toshiba builds 128Mb capacitorless DRAM
Toshiba has fabricated a 128Mb capacitorless DRAM on an SOI wafer and verified operation of the chip.
2005-06-29 SOI embedded DRAM company raises $16 million
Innovative Silicon Inc., a developer of an embedded memory based on floating the body voltage for transistors implemented using silicon-on-insulator CMOS processes, said that Austin Ventures has joined with existing investors to lead a $16.0 million Series B round of investment in the company.
2002-02-12 Scaling debate stalks chip conference
From the wide range of panels and tutorials at the International Solid-State Circuits Conference, from the myriad papers, from the conversations in the hotel halls, a single gnawing issue grew from hints and whispers to a groundswell of concern: Will IC technology continue to scale?
2006-08-16 MRAM ushers in era of new memory tech
For the past 11 years, Saied Tehrani and the MRAM development team he directs at Freescale Semiconductor's Arizona facility have worked on a new type of IC memoryone using magnetic resistance instead of charge storage.
2013-02-11 Memory test tip: Alternative NVM options (Part 1)
Learn about the search for alternative NVM technologies caused by the growing concern that floating-gate flash memory would soon no longer be able to satisfy the requirements.
2006-01-31 Intel tips 45nm process, demos chips
Intel disclosed initial details of its 45nm process. Dubbed P1266, the process incorporates copper interconnects, low-k dielectrics, strained silicon and other features.
2007-02-19 IBM to put 48Mbytes on next-gen microprocessor
By combining techniques in process and circuit design, IBM believes it can put as much as 48Mbytes of fast DRAM on a reasonably sized CPU when its 45nm technology becomes available in 2008.
2006-08-23 Hot Chips conference showcases high-performance architectures
The 18th annual Hot Chips conference featured presentations on the latest multicore solutions for servers and workstations and highly parallel processors for embedded apps.
2005-03-16 Hope floats for new DRAM
A potentially revolutionary 90nm DRAM technology, claiming gains in speed, size and power consumption, has been developed by a Swiss startup.
2012-12-04 Globalfoundries ready to roll out FinFET wafers
The chip making giant's first multi-project wafer runs, which are aimed at customers testing their 14nm FinFET manufacturing process technology, could start as soon as the first quarter of 2013
2009-02-12 Five ways to beat IC scaling roadblocks
Intel senior fellow and director of process architecture Mark Bohr listed five major stumbling blocksor challengesfor the 32nm node and beyond.
2013-06-12 DRAM makers find new processes for sub-nm DRAM cells
TechInsights studied the processes and device architectures of mass-produced 3xnm SDRAM cell array structures from major manufacturers and found that the technologies can be scaled further.
2004-07-30 Design myths surround strained SOI
Whether strained silicon or strained SOI is used has little effect on the 90nm design side.
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