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2005-09-23 Synopsys unveils its latest floorplanning, analysis solution
Synopsys extended its floorplanning solution with the introduction of JupiterIOan enabling technology for concurrent die and package floorplanning and analysis that targets flip chip design flows.
2005-03-16 IC floorplanning moves ahead with Patoma
A new approach to IC floorplanning is said to reduce wire length while running orders of magnitude faster than previous solutions.
2007-07-11 RTL synthesis tool eases chip-level interconnect design
Claiming a new approach that helps solve problems with chip-level interconnect, Cadence Design Systems is announcing a new component of its RTL synthesis tool, the Cadence Logic Design Team Solution.
2001-05-01 Power distribution for deep-submicron SoC designs
Power grid verification is becoming an imperative in deep-submicron design.
2003-12-02 FPGA tool startup tackles ASIC prototyping
FPGA tool startup Hier Design Inc. has announced enhancements to its PlanAhead software that help make it more appropriate for ASIC prototyping.
2003-01-09 EDA's unique opportunity in the silicon value chain
As design sizes shrink toward 90nm, a new set of problems has arisen. Signal integrity, design for test, verification, and design reuse are becoming ever more critical in addressing today's increasing design complexities.
2004-10-07 EDA growth turns anemic in second quarter
Judging from the latest EDA Consortium (EDAC) Market Statistics Survey report, the long-awaited EDA recovery is nowhere in sight.
2005-11-01 Die, package design get closer
Targeting designs headed for flip-chip packages, Synopsys' floor-planning and analysis tool enables concurrent die and package design flows.
2004-12-01 Chip2Nite upgrade promises design time reduction
Silicon Dimensions is announcing an updated release of Chip2Nite, an IC design tool that provides floorplanning, placement, analysis and optimization for logic designers.
2000-06-21 Using Select-RAM Memory in XC4000 Series FPGAs
This application note describes how to implement Select-RAM memory in XC4000 Series design: in schematic entry, MemGen memory block generator, X-BLOX schematic-based synthesis, and HDL-synthesis environments. It also describes specifying timing requirements, evaluating performance and floorplanning.
2000-06-21 Using Select-RAM Memory in XC4000 Series FPGAs
This application note describes how to implement Select-RAM memory in XC4000 Series design: in schematic entry, MemGen memory block generator, X-BLOX schematic-based synthesis, and HDL-synthesis environments. It also describes specifying timing requirements, evaluating performance and floorplanning.
2001-05-01 The need for an EDA API
There are a lot of skepticism with Cadence's IE (Integration Ensemble) tool-with capabilities that include floorplanning, RTL synthesis, placement, routing, extraction and analysis. The arguments for a single tool that encompasses all these features are compelling, but will the tools live up to engineer's expectations?
2011-09-27 A primer on 3D-IC design challenges
Know the 3D-IC design challenges such as system exploration, floorplanning, analysis, and design for test (DFT), and learn how designs will evolve as 3D-IC goes on to become a necessity for managing power, performance, form factor, and cost goals.
2006-08-30 Xilinx upgrades PlanAhead 8.2 analysis software
Xilinx took the wraps off the 8.2 version of its PlanAhead hierarchical design and analysis software with support for its newest Virtex-5 LX family of 65nm FPGAs.
2007-02-05 Xilinx upgrades free ISE Webpack design suite
Xilinx has announced the immediate availability of the ISE WebPACK 9.1i release, the latest version of the company's free downloadable programmable logic design suite.
2006-09-06 Xilinx upgrades analysis software to support 65nm FPGAs
Xilinx has announced the immediate availability of the 8.2 version of its PlanAhead hierarchical design and analysis software with support for the company's newest Virtex-5 LX family of 65nm FPGAs.
2006-11-06 Xilinx unveils new design solution for Virtex-5 LXT
Xilinx announced the availability of a complete logic design solution including an update to its ISE design tools for their newest Virtex-5 LXT Platform FPGAs.
2006-07-07 Xilinx unveils design tools for 65nm Virtex-5 FPGAs
Xilinx has announced the latest release of its design solution, the 8.2i ISE tool suite, now supporting the company's newest line of 65nm Virtex-5 domain-optimized FPGAs.
2007-01-18 Xilinx ISE upgrade shortens FPGA design cycles
Xilinx' ISE 9.1i design suite is optimized to meet today's leading design challenges: timing closure, productivity and power.
2008-03-26 Xilinx design tools suit logic, embedded, DSP
Xilinx has introduced its ISE Design Suite 10.1, a single unified release providing FPGA logic, embedded and DSP designers with immediate access to the company's entire line of design tools with full interoperability.
2006-06-29 Xilinx delivers design solution for 65nm FPGAs
Xilinx has released the 8.2i Integrated Software Environment (ISE) design solution supporting the company's 65nm Virtex-5 FPGAs.
2006-08-30 Toshiba tapeouts 90nm IC with Synopsys compiler
Synopsys announced that Toshiba has used the Synopsys IC Compiler physical implementation solution to tape out its next-generation TC90515XBG home digital network chip.
2003-03-07 Telairity, Icinergy find synergy
Telairity Corp. will use Icinergy's SoCarchitect as part of its recommended flow.
2005-11-23 Synopsys, UMC partner on low power 90nm reference flow
EDA giant Synopsys Inc. and Taiwanese foundry United Microelectronics Corp. (UMC) Monday (Nov. 21) announced the availability of a 90nm reference design flow that is said to be optimized for low-power system-on-chip (SoC) designs.
2007-11-09 Synopsys, UMC co-develop 65nm reference flow
Synopsys and UMC have co-developed a 65nm hierarchical, multivoltage RTL-to-GDSII reference design flow.
2015-11-11 Synopsys, GlobalFoundries team up for 22nm FD-SOI sol'n
The Synopsys Galaxy Design Platform, enabled for the GlobalFoundries' 22FDX platform, claims to offer FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies.
2008-09-25 Synopsys ventures on analog/mixed-signal tools
Synopsys has officially embarked on the realm of analog/mixed-signal design tools with the launching of Galaxy Custom Designer.
2004-12-30 Synopsys shift caused EDA decline, analysts say
A move by Synopsys towards subscription licenses was the primary reason for the EDA industry's revenue decline in the third quarter of 2004, according to two analysts.
2004-10-14 Synopsys says it will shelve Monterey's tools
In confirming earlier reports of its acquisition of Monterey Design Systems, Synopsys Inc. said it will acquire most of Monterey's assets except customer contracts and will shelve all existing Monterey tools.
2006-06-29 Synopsys rolls out 2006.06 version of IC Compiler
Top tier EDA vendor Synopsys Inc. recently rolled out the last version of its next-generation place-and-route tool, IC Compiler.
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