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2005-04-01 Is EDA's world too provincial?
If EDA wants to come out of its current stagnation, it may be time to broaden the focus.
2005-03-10 IBM EDA tools emerge from Europe's Prosyd project
One year after the launch of the Prosyd collaborative research project between IBM Corp., Infineon Technologies AG and STMicroelectronics NV with about 4 million euros (about $5.3 million) of European tax payers' money, the project has helped IBM produce chip design verification tools.
2009-03-02 Verification tools receive upgrades
Jasper Design Automation's ActiveDesign with behavioral indexing is an IC design tool billed as enabling design engineers to capture and preserve intended design behavior as it is being implemented
2003-08-26 TransEDA proposes asset sale to Valiosys
Struggling British EDA firm TransEDA Ltd has announced its intent to sell all its assets to French formal verification firm Valiosys S.A. for ?1.15M
2007-10-31 Startup rolls automated device driver generator
Vayavya Labs is launching an automated device driver generator framework that the company claims will bring discipline through its formal language-based approach
2005-01-21 Startup claims to optimize IC layouts for yield
Even the best chip layouts need some help to maximize IC yields, according to startup Nannor Technologies Inc., which is quietly preparing a layout optimization tool
2008-02-26 Rhines on EDA: End 'endless verification'
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification
2003-05-30 O-In offers 'unified coverage' metric
Claiming to offer the first metric that measures verification in both simulation and formal tools, 0-In Design Automation has announced a &quot:unified coverage" metric called structural coverage
2014-03-27 Lean NPI solution automates PCB design and manufacturing
The Mentor Graphics Valor NPI software product helps NPI engineers prepare and validate product models according to the manufacturer's rule-set in the engineer's native design tool
2005-05-16 HR management at the sharp end
An appraisal is a tool for managers to use and from which they will benefit. If there is no benefit, then where does the problem lie
2010-08-03 EU's Speculative and Exploratory Design in Systems Engineering (SPEEDS) project concludes
The four-year SPEEDS (SPEculative and Exploratory Design in Systems Engineering) project, funded under the European Union's 6th Framework Programme, has resulted in the definition of a novel end-to-end design methodology, process and tool environment
2012-10-22 Embedded software devt: The disciplined way (Part 2)
Only one tool is needed to make huge improvements in both the quality and delivery time of your next embedded project
2002-05-03 Cadence supports Accellera specification language
Cadence Design Systems Inc. has revealed that it is supporting the standard property specification language defined by Accellera to enable assertion-based simulation and formal verification
2004-12-08 Altera unveils unified design flow
Altera's new design software is claimed to be the industry's first and only tool to offer a unified design flow for the development of FPGAs, CPLDs and structured ASICs
2003-11-13 0-In assertion compiler has multilingual features
The company will announce an enhanced assertion compiler for its Assertion-Based Verification (ABV) tool suite
2013-11-12 Windows XP expiration pushes rethinking of industrial op'n
The extended support and availability of security updates for Windows XP will end in April 2014, driving asset owners needing to continue secure operation to think about their course of action.
2015-11-23 What makes hardware emulation so compelling
Here is a quick assessment of the evolution of hardware emulators over the past two decades, comparing where things stood in the 90s to where they are today.
2002-03-13 Vendors join push for assertion standards
The strongest effort yet to forge a standard assertion language for IC verification will unfold at the International HDL Conference this week, as Co-Design Automation and Real Intent announce the donation of the Superlog Design Assertion Subset to the Accellera standards body.
2013-09-11 Understanding contract-based programming
Know what contract-based programming is all about, and how it can be used to make software more reliable.
2005-03-25 UMC considers taking 15 percent stake in Chinese fab
Taiwan foundry United Microelectronics Corp. (UMC) said Monday (Mar. 21) it may take a 15 percent stake worth $110 million in Chinese foundry He Jian Technology Corp., possibly with the hope of settling litigation in Taiwan accusing the firm of illegally helping the Chinese company build up its business.
2009-03-03 TSMC details litho roadmap, taps maskless
Taiwan Semiconductor Manufacturing Co. Ltd has detailed it lithography roadmap and said it is still backing maskless technology at the SPIE Advanced Lithography conference.
2003-10-08 TransEDA gets second life under TNI-Valiosys
French embedded software and EDA tools vendor TNI-Valiosys has completed its acquisition of struggling British EDA company TransEDA plc for an undisclosed amount.
2008-01-07 Top 10 stories to keep track this year
ChannelWeb assembled a panel of industry experts comprising vendors, analysts and solution providers to discuss what they think will be the most important chip stories to watch in 2008.
2014-11-20 The ways to verify SoC
In this article, we will start with the discussion on what and why of verification and only then consider the how.
2007-06-18 The intricate dance of cutting power consumption
Key players in the industry are collaborating to deliver low-power solutions that bring more automated EDA tools, smarter IP, standard formats and more power-stingy processes together into true end-to-end solutions. EDA and IP companies have worked within the Accellera standards organization to develop the Unified Power Format (UPF).
2003-03-20 Telelogic forms alliance with research, engineering firm
Telelogic AB has signed an agreement with research and engineering firm Science Applications Int. Corp., to jointly pursue new clients and business prospects of the latter utilizing Telelogic DOORS and other Telelogic application lifecycle management tools.
2002-04-04 Technical program assembled for upcoming DAC
Hoping to convince designers that this year's Design Automation Conference is worth the trek to New Orleans, the show's committees have announced an innovative technical program.
2004-03-16 Synthesis methods for ASIC, FPGA designs
Design methodologies that employ cross-implementation EDA technology such as the MultiPoint provide the flexibility to implement a design in the best possible medium.
2004-02-02 Synopsys, Cadence give nod to SystemVerilog changes
Enhancements based on feedbacks from vendors and users spotlighting some shortcomings in the current ver 3.1, will be implemented in SystemVerilog 3.1a.
2004-02-19 Synopsys, ARM to write SystemVerilog manual
Seeking to write the book on how to use SystemVerilog for verification, Synopsys Inc. and ARM Ltd. are working together on a SystemVerilog Verification Methodology Manual and hope to have it ready by June.
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