Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > formal tool

formal tool Search results

?
?
total search183 articles
2014-09-25 Synopsys platform speeds up time-to-market for advanced SoCs
The Synopsys Verification Continuum introduces Unified Compile with VCS and Unified Debug with Verdi across the verification flow, speeding time-to-market by months for complex SoC designs.
2006-03-22 Synopsys claims first complete SystemVerilog flow
Synopsys laid claim to being the first EDA vendor to provide a complete SystemVerilog flow, saying the language is now supported throughout its suite of design and verification products.
2002-09-01 Startups with new ideas
In spite of industry consolidation and slowing growth rates, EDA startups are bringing new ideas and technology to chip designers.
2004-01-01 Startup promises 'algorithm to tapeout'
Synfora's Pico product line will let users create C-language algorithms for blocks such as MPEG or MP3 decoders.
2004-04-01 Startup aims at DSP algorithm development
Catalytic is targeting the floating- to fixed-point model conversions with an approach that combines EDA with embedded-software development.
2002-06-12 Standards inch forward with skeptics in tow
Two standards efforts will take major steps forward at the 39th Design Automation Conference, as the OpenAccess Coalition announces four additional EDA vendor members and much of the EDA community lines up behind Accellera's new SystemVerilog standard.
2006-03-30 Sequans used Synopsys' tools in WiMAX/WiBro chip development
Synopsys announced that Sequans Communications has adopted key components of the Discovery Verification Platform and standardized on the Synopsys VCS comprehensive RTL verification solution.
2014-01-17 Selecting the optimum coding standard
Find out how to choose the coding standard or subset to use and how to test for compliance.
2002-04-15 Researchers propose dual design verification model
Indian researchers are proposing a novel verification methodology that uses two representations of a design throughout the verification process, one a behavioral model in C and the other an RTL model.
2012-04-25 Reducing cost and size: The software angle
A new approach that combines a reliable language with customizable and specialized run-time libraries can trim both cost and footprint size for embedded systems.
2014-12-15 Probing the macroeconomics side of Moore's Law
The author believes that the entire economic structure that was supposed to lead to next-generation manufacturing technologies like 450mm wafers and EUV lithography is on the verge of coming apart.
2007-03-19 Plan your verification process with SystemVerilog
The best way for the verification team to match the automatic tests with their corresponding design features is via functional coverage metrics.
2007-09-17 Optimal use of assertions in verification
Assertions provide an efficient way of improving overall design cycle productivity by cutting verification time. Here are some tips in the optimal use of assertions in verification.
2003-03-03 Novas adds assertion support to debugger
Novas Software Inc. has added OpenVera assertion support to its new Verdi Behavior-Based Debug System.
2004-10-26 New Synopsys timing model challenges Cadence's ECSM
Seeking a more accurate approach to nanometer delay modeling, Synopsys revealed its composite current source (CCS) model at the Synopsys Interoperability Forum here Thursday (Oct. 21).
2014-02-11 NASA joins 3D manufacturing bandwagon
Given NASA's unique needs for highly customized spacecraft and instrument components, additive manufacturing, or 3D printing, offers a compelling alternative to traditional manufacturing approaches.
2008-08-21 Mentor, Altera propel avionics design with DO-254 IP
Altera Corp. and Mentor Graphics Corp. announced the companies are working together to develop tools and methodologies for use in creating DO-254-certifiable intellectual property that targets Altera's FPGA and HardCopy ASIC solutions.
2003-03-05 Mentor Graphics to develop FPGA verification solution for Thales
Mentor Graphics Corp. has entered into a technology relationship with Xilinx Inc. and Thales Communications to develop a new FPGA verification flow to meet Thales' requirements for its next-generation products.
2008-06-03 Maskless tools to boost ASIC throughputs
E-Shuttle Inc. is set to improve its direct-write e-beam capabilities and explore the future use of next-generation maskless tools from Mapper Lithography NV and other startups in the arena, making e-beam tools a probative technology in mainstream production fabs.
2004-05-19 Lighthouse introduces synthesis tools for Verilog test
Promising to reduce testbench development time by up to 80 percent, startup Lighthouse Design Automation Inc. will introduce tools that synthesize Verilog testbenches from high-level specifications.
2006-02-01 Language standards from IEEE open choices
Once seen as competitors, SystemC and SystemVerilog languages appear to be settling into largely complementary niches.
2004-05-06 Jasper upgrades verification product
Jasper Design Automation will announce the latest release of its JasperGold product enabling what the company calls a provably correct design methodology.
2006-10-04 Industry players meet to discuss standard for Open DFM
Participants of the Open DFM Model Workshop last week explored issues ranging from DFM flows to encryption and identified possible next steps.
2007-02-01 High-speed interconnects reshape board
A handful of high-speed interconnects are driving changes in how designers handle fast signals. The Scalable System Packet Interface from the Optical Internetworking Forum aims to carry data at 6Gbps and up between chips or boards in a communications system.
2014-12-01 Examining ISO 26262 from a developer's viewpoint
Here's an overview of the standard from system designer and implementer's viewpoint. It is based on QNX Software System's recent experience certifying its operating system to ISO 26262.
2007-04-16 Equivalence checker supports FPGA optimizations
Startup OneSpin Solutions GmbH has introduced a solution that makes FPGA equivalence checking practical by supporting those optimizations.
2006-11-08 Equivalence checker eyes clock gating
The sequential equivalence checker that Calypto Design Systems will release soon promises to automate the verification of clock-gating circuitry.
2014-11-06 Enhance SoC efficiency with multi-bit flip-flops
Here's a look at the architecture of multi-bit flip-flops, its merits and drawbacks. It also tackles the results of its implementation in a particular design and the various areas of concern.
2014-02-13 Energy design through unified hardware abstraction
Learn how to achieve energy-efficient solutions through optimal alignment across the pre- and post-silicon phases of energy optimisation supported by unified design flows, abstractions and formats.
2012-07-12 Employ emulation to debug software and hardware at the same time
Here's a guide to using an emulator to ensure the system is truly ready to be committed to silicon.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top