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2002-04-22 TransEDA licenses formal-verification technology from SRI
Making a concerted effort to be seen as more than a simulation add-on tool vendor, TransEDA plc has licensed raw formal-verification technology from Stanford Research Institute and plans to turn this know-how into formal and semiformal verification tools within a year.
2007-09-20 Taiwan's MediaTek adopts Mentor's formal verification tech
Mentor Graphics announced that Taiwan's MediaTek has selected the 0-In formal verification technology to make it an integral part of its verification flow for their next generation design projects.
2014-03-07 Synopsys unveils verification compiler sol'n
The Verification Compiler is a portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure
2003-03-05 Mentor Graphics to develop FPGA verification solution for Thales
Mentor Graphics Corp. has entered into a technology relationship with Xilinx Inc. and Thales Communications to develop a new FPGA verification flow to meet Thales' requirements for its next-generation products
2004-06-01 Jasper upgrades verification product
Jasper has announced its JasperGold product that enables what the company calls a "provably correct design" methodology.
2004-05-06 Jasper upgrades verification product
Jasper Design Automation will announce the latest release of its JasperGold product enabling what the company calls a provably correct design methodology.
2004-07-01 Jasper upgrades verification product
The company has announced the latest JasperGold product enabling what Jasper calls a "provably correct design" methodology.
2004-11-18 Cadence Encounter Conformal 5.0 with enhanced verification capability
Cadence Design Systems announced enhancements to its Encounter Conformal technology
2010-06-08 Tools offer shared database for design, verification
From Jasper Design Automation come improved versions of the ActiveDesign and JasperGold tools with capabilities that bridge the divide between chip design and verification by sharing common database
2003-06-27 Synopsys strengthens verification efforts with acquisition
Synopsys Inc. has acquired InnoLogic Systems Inc., a provider of memory and full-custom equivalence checking technology
2003-01-21 Synopsys moves customers to verification area
Synopsys Inc. hopes to hold on to a slight lead in the formal verification market as it moves customers from the Design Verifyer tool to its internally developed Formality equivalence checker
2002-10-15 Swedish startup eases use of formal tools
Startup Safelogic is rolling out a formal property checker and a simulation "plug-in" for property monitoring
2007-06-14 Simulink design suite adds formal methods
Adding formal design methods to its widely used Simulink model-based design suite, The Mathworks Inc. has introduced the Simulink Design Verifier, which generates tests and proves properties for models from the company's Simulink simulation platform and Stateflow design and simulation tool
2008-02-26 Rhines on EDA: End 'endless verification
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification
2005-03-28 Renesas integrates Mentor's 0-In for assertion based verification flow
Renesas Technology Corp. has completed the integration of Mentor Graphics Corp.'s 0-In assertion synthesis technology and assertion-based verification flows with Renesas' LogicBench rapid prototyping system
2010-12-17 Proof kits enable faster, accurate SoC verification
Jasper Intelligent Proof Kits encapsulate critical behaviors for popular protocols such as ARM’s AMBA, allowing users to quickly configure designs to the standard or adapt them to their own custom configuration. These kits are optimized for high-level verification with Jasper’s ActiveDesign and JasperGold formal verification
2003-07-03 PLX, Jasper partner on formal verification solution
PLX Technology Inc. and Jasper Design Automation have collaborated to bring formal verification to PLX chips based on PCI Express technology, via the JasperGold formal verification tool.
2002-03-27 Novas readies behavior-based debugging technology
Novas Software Inc. is preparing a behavior-based debugging technology that it says will support higher levels of abstraction, and is also promising improved performance and new "knowledge management" capabilities for the upgrade of its Debussy HDL debugging tool
2004-12-01 Methodology sought for assertion-based verification
Silicon IP providers and creators seek guidelines on how to use assertions effectively, aside from the standard protocols.
2003-06-16 Memory verification needs fresh approach
By interpreting parameter values corresponding to the implementation structure, equivalence-checking comparisons between RT and transistor level can be easily accomplished.
2003-06-10 Formal tools won't replace simulation
Formal verification is a valuable adjunct to simulation, but not a replacement for it, according to panelists at the Design Automation Conference
2007-09-24 Firms collaborate to address 65nm FPGA design verification
Xilinx Inc. and a group of EDA companies teamed up to define and implement new verification flows to address ultrahigh-density designs of 65nm FPGAs and new emerging FPGA architectures
2005-06-14 Emerging DFM, verification technologies most exciting, CTOs say
Emerging technologies for design for manufacturing (DFM) and verification are the most exciting developments in the design realm, concluded a panel of chief technology officers convened here Monday (June 13) at the Design Automation Conference (DAC
2007-04-25 Device-native verification tool rolls for FPGAs
Startup GateRocket has rolled out a device-native FPGA verification solution that includes hardware and software
2006-06-01 Breaking the verification barrier
Startup OneSpin Solutions believes it has technology that will usher in a new era of IC formal verification. But if this company is successful, the real breakthrough may be one of bringing internal technology from a large integrated device manufacturer into a global, commercial EDA market.
2013-01-02 Apply formal methods to power-aware verification
Read about an apps approach for implementing formal methods to power-aware verification
2007-02-01 Accellera to define verification coverage metrics
Responding to user calls for a consistent way to measure functional-verification completeness, the Accellera standards organization has launched the Unified Coverage Interoperability to define standards that enable the sharing and analysis of coverage data by different tools during the verification process
2003-01-31 0-In pumps up assertion-based verification suite
Armed with two new products and new technology, 0-In Design Automation is rolling out version 2.0 of its assertion-based verification suite
2009-03-02 Verification tools receive upgrades
Jasper Design Automation's ActiveDesign with behavioral indexing is an IC design tool billed as enabling design engineers to capture and preserve intended design behavior as it is being implemented.
2002-07-10 Verification startup wants everyone to go 'formal
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