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2001-05-24 Using formality in LSI Logic's FlexStream design flow
This application describes procedures and recommendations for using the Formality formal equivalence checking tool for Gate to Gate equivalence checking.
2001-05-24 Using formality for RTL-to-gate in LSI Logic's FlexStream design flow
This application note describes procedures and recommendations for using the Formality formal equivalence checking tool for RTL-to-gate equivalence checking.
2003-01-21 Synopsys moves customers to verification area
Synopsys Inc. hopes to hold on to a slight lead in the formal verification market as it moves customers from the Design Verifyer tool to its internally developed Formality equivalence checker.
2004-06-17 Synopsys low-power solution supports 90nm designs
During the DAC 2004, Synopsys announced that its Galaxy Power offers the industry's first comprehensive low-power solution for today's advanced, high-performance 90nm designs.
2002-03-20 Synopsys gives equivalency checker a new look
In an effort to make formal equivalency checking more accessible to designers who aren't formal-verification experts, Synopsys has rolled out a "flow-based" user interface for its Formality tool.
2007-04-24 Synthesis solution boosts IC performance
Synopsys released the Design Compiler 2007 synthesis solution, which extends topographical technology to accelerate design closure for designs utilizing advanced low-power and test techniques, to boost designer productivity and IC performance.
2015-11-11 Synopsys, GlobalFoundries team up for 22nm FD-SOI sol'n
The Synopsys Galaxy Design Platform, enabled for the GlobalFoundries' 22FDX platform, claims to offer FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies.
2005-07-29 Synopsys test methodologies verify SLE's chip developments
Synopsys Inc. announced that its VCS comprehensive RTL verification solution and Vera testbench automation tool have been adopted by ASIC design services provider Silicon Logic Engineering (SLE) to accelerate its chip development process.
2004-03-18 Synopsys takes another stab at FPGA synthesis
Synopsys has tweaked its Design Compiler ASIC synthesis tool to enable designers to use the same tools and potentially the same design flow for ASICs and FPGAs.
2004-11-23 Synopsys supports Xeon processor with Intel EM64T
Synopsys Inc. claimed to be the first EDA software company to support the Intel Xeon processor with Intel Extended Memory 64 Technology (Intel EM64T) for 64bit and 32bit computing with the Red Hat Enterprise Linux version 3 operating system using its Galaxy design and Discovery verification technology.
2005-02-09 Synopsys supports SUSE LINUX with verification platform
Synopsys Inc. will support the SUSE LINUX Enterprise Server 9 operating system (OS) from Novell on both 32bit and 64bit x86 instruction sets for Synopsys' Galaxy Design and Discovery verification platforms.
2004-09-03 Synopsys solutions to support IPCore design flow
Synopsys Inc. disclosed that China-based IPCore Technologies Corp. has signed a multi-million dollar agreement.
2004-11-25 Synopsys offers support to Intel processor with EM64T
Synopsys said it is the first EDA software company to support the Intel Xeon processor with Intel EM64T for 64- and 32bit computing.
2004-04-06 Synopsys forum updates SystemVerilog support
The message at the Synopsys EDA Interoperability Developer's Forum, convening Thursday (April 1, 2004), is clear; SystemVerilog support is growing.
2004-12-27 Synopsys ESP speeds verification of Metro platform memories
Synopsys Inc. announced that Artisan Components Inc. has standardized its ESP full-custom memory equivalency checker for the latest low-power, high-density Metro Platform memories.
2004-10-05 Synopsys DC FPGA supports Xilinx FPGAs, software
The Design Compiler FPGA from Synopsys now supports Xilinx's Virtex-4 family of domain optimized FPGAs and ISE 6.3i place and route software.
2006-03-22 Synopsys claims first complete SystemVerilog flow
Synopsys laid claim to being the first EDA vendor to provide a complete SystemVerilog flow, saying the language is now supported throughout its suite of design and verification products.
2006-03-30 Sequans used Synopsys' tools in WiMAX/WiBro chip development
Synopsys announced that Sequans Communications has adopted key components of the Discovery Verification Platform and standardized on the Synopsys VCS comprehensive RTL verification solution.
2005-10-07 New design flow for ARM Cortex-A8 processor from Synopsys
Synopsys and ARM demonstrated the successful integration of Synopsys' Galaxy RTL synthesis, hierarchical design planning, physical implementation solution, sign-off and Discovery verification solution within a high-performance design flow for the new ARM Cortex-A8 processor.
2016-01-25 Is Xilinx set to jump on the M&A bandwagon?
The company made a filing with the U.S. SEC pertaining to executive benefits in the event of change of ownership of the company, fueling speculation that the FPGA leader is preparing to be acquired.
2003-03-10 India relaxes its rules on foreign telecom ownership
Overseas companies will soon be allowed to hold majority equity stakes in India's telecommunication service providers, both fixed-line and mobile.
2006-06-01 IEEE standardizes 'e' language
The IEEE has put its stamp of approval on Cadence Design Systems Inc.'s "e" verification language, making it an open standard that anyone can use or support.
2006-10-18 Hua Hong NEC, Synopsys team up for reference design
Synopsys and Hua Hong NEC announced their jointly developed Reference Design Flow 2.0 for Hua Hong NEC's 0.18?m process.
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