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2015-11-23 What makes hardware emulation so compelling
Here is a quick assessment of the evolution of hardware emulators over the past two decades, comparing where things stood in the 90s to where they are today
2013-10-08 Kozio unveils versatile hardware verification solution
Kozio has developed a special verification and test OS called VTOS that has a small memory footprint and boasts fast load times.
2006-06-01 IEEE standardizes 'e' language
The IEEE has put its stamp of approval on Cadence Design Systems Inc.'s "e" verification language, making it an open standard that anyone can use or support
2015-02-09 Hardware emulation: The most versatile of them all
Nowadays, one of the most popular verification tools is hardware emulation and it might remain so in the next few years. Here is a look at the reasons behind its eminent success
2015-09-08 Examining performance in hardware emulators
Emulation performanceor the speed of its executiondepends on the architecture of the emulation system and the type of deployment.
2015-04-24 Examining OS as the hub of hardware emulator
The operating system shields the software from the hardware and assures the compatibility of any new and old software with any new or old hardware platform
2002-08-09 Engineer creates open-source HDL in Ruby language
Illustrating the power of the Ruby scripting language, consulting engineer Phil Tomson has used it to create the open-source Ruby hardware-description language.
2002-05-03 Cadence supports Accellera specification language
Cadence Design Systems Inc. has revealed that it is supporting the standard property specification language defined by Accellera to enable assertion-based simulation and formal verification
2005-01-31 Back to the language roots
Although SystemC has its place in the hardware-design process, it still can't compete with Verilog and VHDL
2015-08-28 Agile techniques for hardware design (Part 3
In the final instalment of this Agile Hardware article, we will describe Chisel, a new programming tool suitable for Agile hardware development
2004-06-16 Hardware holds value for classifying packets
Explore the growing value of hardware, including programmable state machines and discrete coprocessors, in developing secure applications
2001-05-01 FPGA tools need hardware assistance
While techniques such as logic emulation provide a new tool for logic designers, many other FPGA-based systems serve as high-performance replacements for standard computers.
2003-06-02 Combine hardware and software design in programmable SoC
SCSD is a methodology converging hardware and software techniques, providing a cohesive path from system specification and functional algorithm identification to system implementation
2015-08-26 Agile techniques for hardware design (Part 2
In Part 2 of this Agile Hardware article, we will reveal the actual costs, and discuss the implications for Agile hardware development
2015-03-26 Understanding design compilation in hardware emulators
Design capacity in hardware emulators, also the compilation flow, is heavily dependent on the type of technology utilised in the verification engine
2016-03-24 Explore model-based testing for production hardware
Here is a look at Time Partition Testing, a model-based testing technique, which is based on hybrid, hierarchical, parallel running automatons with continuous behaviour.
2008-07-08 Debugging a shared memory problem in multicore with virtual hardware
Over the past few years, the virtual hardware platform concept has emerged as a key new capability for software developers to improve their ability to debug software applications
2012-10-11 Verification debugger cuts op'n time by 40%
The Incisive Debug Analyser allows users to step forward or backward through their hardware verification language (HVL) and hardware description language (HDL).
2005-05-11 Verific Design licenses HDL component software to Calypto
Calypto Design Systems Inc. has licensed Verific Design Automation's hardware description language (HDL) component software.
2002-08-30 Synopsys to acquire IC design verification firm
Synopsys Inc. has signed a definitive agreement to acquire all outstanding shares of Co-Design Automation
2003-05-02 Speeding up DSP solutions with FPGAs
Even though today's DSPs are fast and are useful for many applications, there are applications out there that need a little extra boost of performance - and FPGAs provide increased performance.
2005-06-06 Renesas selects Verific HDL component software
Renesas Technology Corp. has adopted Verific Design Automation's hardware description language (HDL) component software for use in its internal EDA environment
2007-02-06 Regaining ESL credibility
Credible ESL companies have to fight the unfortunate reputation bestowed upon them by the mere fact that they are part of an industry that's been in existence for quite some time, but has accomplished little.
2007-11-23 Mentor tips optimized FPGA design flow
Mentor Graphics has announced support for hardware description language (HDL) generated by MathWorks Simulink HDL Coder in the its Precision suite of advanced synthesis products.
2004-07-19 Mentor Graphics releases tools for systems with 64-bit Linux
Mentor Graphics released a design-to-silicon platform and a hardware description language simulator for AMD64 processor-based systems running 64-bit Linux.
2015-07-20 HIL simulation for hybrid powertrain test
In this article, we explore how development of motor ECUs can be accelerated substantially through the application of hardware-in-the-loop methods
2001-03-20 Getting started converting .ABL files to VHDL
This application note is intended to assist Warp users in converting designs written in DATA I/O's ABEL 7 HDL to IEEE 1076 VHDL.
2005-12-06 Forte, Summit team up on design and verification flow
Forte Design Systems and Summit Design announced their collaboration to deliver an integrated solution that combines the strengths of the Vista SystemC IDE and Cynthesizer SystemC synthesis products.
2012-04-30 Design for power methodology: From architectural plan to signoff
Here's a look at a holistic design for power methodology that spans from architectural decisions through front-end design to physical implementation and sign-off.
1999-11-19 Concurrent ASIC design flows
This paper presents techniques that would be the stepping stone to a better design methodology. The discussion will be presented in two phases: batch design flows, and concurrent design flows.
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