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2015-11-23 What makes hardware emulation so compelling
Here is a quick assessment of the evolution of hardware emulators over the past two decades, comparing where things stood in the 90s to where they are today
2004-01-01 Verification platform for Jeda language rolls
Jeda Technologies released Jeda-X, a commercial product based on the Jeda hardware verification language.
2012-10-11 Verification debugger cuts op'n time by 40
The Incisive Debug Analyser allows users to step forward or backward through their hardware verification language (HVL) and hardware description language (HDL).
2003-11-13 New verification platform is based on Jeda language
New verification platform is based on Jeda language
2015-02-09 Hardware emulation: The most versatile of them all
Nowadays, one of the most popular verification tools is hardware emulation and it might remain so in the next few years. Here is a look at the reasons behind its eminent success
2015-09-08 Examining performance in hardware emulators
Emulation performanceor the speed of its executiondepends on the architecture of the emulation system and the type of deployment.
2007-06-18 Define your verification plan with SystemVerilog
The adoption of constrained random testbenches, functional coverage and assertions fits seamlessly with embracing SystemVerilog. The value of these technologies is enhanced with an evolution of the verification planning process from simple test plans to VPA-driven verification plans
2006-09-06 Website offers free open source C++ IC verification tools
Two engineers have launched a website with open-source tools that can help IC verification teams with C++ verification
2006-01-02 SystemVerilog won't kill 'e' language
Backers of 'e,' which is nearing IEEE standardization, say that rumors of the language's death are exaggerated
2005-09-30 Synopsys testbench solution increases verification productivity
Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs
2006-10-16 Open-source tools ease C++ verification
Two engineers published a book on IC verification with C++ and launched a website with free open-source tools that can help IC verification teams
2013-10-08 Kozio unveils versatile hardware verification solution
Kozio has developed a special verification and test OS called VTOS that has a small memory footprint and boasts fast load times
2005-01-17 Inside a hybrid verification model
The combination of languages, tools, IP and methodologies has morphed the traditional ASIC design cycle into a 'hybrid model' process. Learn more.
2006-06-01 IEEE standardizes 'e' language
The IEEE has put its stamp of approval on Cadence Design Systems Inc.'s "e" verification language, making it an open standard that anyone can use or support
2015-04-24 Examining OS as the hub of hardware emulator
The operating system shields the software from the hardware and assures the compatibility of any new and old software with any new or old hardware platform
2012-08-13 Equip hardware engineers with right tools, processes
Find out why the hardware engineer should be empowered with the right tools and processes for a critical design phasethe arrival of the prototype
2015-05-15 Enhancing analogue design verification using UVM
In this article, we explore an efficient, reusable analogue and mixed-signal verification approach using the Universal Verification Methodology
2007-03-14 Co-verification solution rolls for Actel FPGAs
Aldec has announced the release of CoVer, a Windows-based HW/SW co-verification solution for Actel's ARM-based FPGAs
2007-02-23 C++ verification class library rolls for SystemC
Filling what it sees as missing capabilities in the SystemC verification environment, Jeda Technologies is introducing NSCv, a C++ verification class library for SystemC
2014-06-05 Accellera updates Verilog-AMS with verification, modelling
The enhanced features of Verilog-AMS 2.4 include supply sensitive connect modules, an analogue event type to enable efficient electrical-to-real conversion and current checker modules.
2013-07-22 Virtual design, verification for e-Mobility
Learn how to address many of the emerging engineering challenges that carmakers now face.
2004-06-09 Verisity eyes 10x verification boost with VPA
Verisity hopes to address the growing complexity in IC development with a series of applications for both engineering-level and project-level problems.
2001-04-15 Verification firm starts partners program
Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry.
2008-06-02 Use system models for better verification
This article describes the system-level to RTL design and verification flow of a commercial graphics processing chip. In this flow, system models were developed to validate the arithmetic computation of video instructions and were then used to verify the RTL implementation using sequential logic equivalence checking
2015-03-26 Understanding design compilation in hardware emulators
Design capacity in hardware emulators, also the compilation flow, is heavily dependent on the type of technology utilised in the verification engine
2007-03-16 Take distinctive approach to IC verification
Richard Goering spoke with Hooman Moshar about Broadcom's distinctive approach to IC verification
2002-08-30 Synopsys to acquire IC design verification firm
Synopsys Inc. has signed a definitive agreement to acquire all outstanding shares of Co-Design Automation
2010-01-15 Parallel language, early verification to drive 2010 success
According Mathworks India Pvt. Ltd managing director, Kishore Rao, parallel language and early verification with Model-Based Design will serve as cornerstones of engineering success in 2010
2007-09-17 Optimal use of assertions in verification
Assertions provide an efficient way of improving overall design cycle productivity by cutting verification time. Here are some tips in the optimal use of assertions in verification
2003-10-29 Mentor launches 'scalable' verification platform
Armed with new technologies supporting design-for-verification, Mentor Graphics Corp. has rolled out its Scalable Verification platform
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