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2014-01-15 Cadence unveils Incisive 13.2 for SoC verification
The Incisive 13.2 platform from Cadence Design Systems offers features two new engines and additional automation features to speed SoC verification closure.
2012-10-11 Verification debugger cuts op'n time by 40%
The Incisive Debug Analyser allows users to step forward or backward through their hardware verification language (HVL) and hardware description language (HDL).
2005-03-16 Transaction-based simulation using SystemC/SCV
Learn how SystemC/SCV speeds up simulation and verification cycles to provide overall project cycle with better quality results
2006-06-16 Novices get IC picture
Part of Cadence's top-tier Incisive Enterprise tool suite, the Scenario Builder lets designers with limited verification expertise craft multichannel, system-level verification scenarios.
2003-03-05 Cadence verification platform has unified methodology
Cadence Design Systems Inc. has launched its Incisive verification platform that supports a unified verification methodology for the embedded software, control, data path, and analog/mixed-signal/RF design domains.
2006-09-14 Cadence tool seen to hasten hardware assistance adoption
Cadence Design Systems believes its next-generation series of Incisive Xtreme accelerators/emulators can remove the traditional barriers to mass adoption of hardware assistance by design teams.
2006-06-15 Cadence offers 'first' transaction-based system verification
Cadence unveils 'first' automated end-to-end transaction-based system verification and management solution.
2004-09-03 Cadence emphasizes solutions in design tech symposium
As part of a promotional campaign of its portfolio in Southeast Asia, Cadence Design Systems showcased different versions of its electronics design software solutions in a design technology symposium held in Manila, Philippines, in Aug. 24.
2007-08-02 Winbond adopts Cadence emulator to ease verification
Cadence Design Systems announced that Winbond Israel has adopted the Cadence Incisive Palladium emulator system for its advanced system-level verification needs.
2011-02-09 Synopsis launches verification migration program
Synopsys has launched its verification FastForward migration program and invited Cadence Incisive and Mentor Questa users to join.
2004-06-03 Cadence, CoWare partner on ESL-to-RTL verification
Last September's partnership between CoWare Inc. and Cadence Design Systems Inc. has yielded its first fruits, as the companies are introducing a new co-developed flow they claim will allow users of CoWare's ConvergenSC SystemC-based prototyping system to "seamlessly" transfer models built in SystemC and Verilog to Cadence's Incisive verification platform.
2004-10-22 Cadence to add assertion library to platform
Cadence said it will add new assertion-based verification functionality and a new ABV library to its Incisive verification platform's Unified Simulator.
2004-10-21 Cadence to add assertion library to platform
Cadence Design Systems Inc. said it will add new assertion-based verification (ABV) functionality and a new ABV library to its Incisive verification platform's Unified Simulator.
2004-10-25 Cadence releases next-gen HW-based verification system
Cadence Design Systems Inc. released its Palladium II system, an integral part of the company's Incisive functional verification platform.
2005-05-04 Cadence formal analysis claims ease of use
Cadence Design Systems is introducing this week Incisive Formal Verifier, a tool that aims to make it easy for IC designers verify assertions in RTL code.
2004-12-30 ABV solution speeds verification of complex designs
Cadence announced a comprehensive assertion-based verification solution as a part of its Incisive functional verification platform.
2006-10-04 Yogitech unveils 'first' Open Core Protocol UVC
Yogitech, a provider of design and verification technology, announced what it touts as the industry's first mixed-language Open Core Protocol universal verification component.
2005-03-21 Wipro, Cadence renew EDA agreement
Tapping into a growing Indian IC design market, Cadence Design Systems Inc. has renewed an agreement giving India-based Wipro Technologies access to its EDA software.
2007-07-16 Verify designs with assertions
When adopting components of assertion-based verification (ABV) into standard production flows, teams run into several challenges. This article gives tips and tricks when dealing with ABV.
2007-08-29 Verification kit supports advanced techniques
Cadence Design Systems' new verification kit for SoC designs that aims to enable engineers to adopt advanced verification techniques with reduced risk and deployment effort.
2006-01-02 SystemVerilog won't kill 'e' language
Backers of 'e,' which is nearing IEEE standardization, say that rumors of the language's death are exaggerated.
2009-03-18 Solution supports on-chip power management
Cadence Design Systems Inc. has enhanced the Cadence Low-Power Solution to include support for new on-chip power management schemes enabled by the recently ratified Si2 Common Power Format (CPF) Version 1.1.
2009-05-25 Software tools speed up design process
EDA software vendor Cadence Design Systems has introduced two tools aiming at speeding up the design process.
2010-12-06 SMIC chooses Cadence for 65-nm reference flow
Cadence Design Systems, Inc., has just announced that SMIC has adopted Cadence Silicon Realization products for the DFM and low-power technology at the center of SMIC's 65-nanometer Reference Flow 4.1.
2011-06-08 Simulation tool offers Xilinx FPGA verification
MathWorks announced the availability of its EDA Simulator Link 3.3 with new FPGA-in-the-loop capabilities for Xilinx FPGA development boards to help engineers verify their designs at hardware speeds.
2013-01-25 Reduce power estimation time from weeks to hours
Find out how to automatically generate a chip design's gate-level waveform from the RTL design environment without having to bring up the gate-level environment.
2007-09-06 Rambus, Cadence partner on verified PCIe solutions
Rambus and Cadence Design Systems have collaborated to develop fully integrated and independently verified PCIe solutions.
2011-11-03 Perform assertion-based verification in mixed-signal design
Understand how assertion-based verification can address the challenges in analog/mixed-signal verification.
2008-12-09 Open source SystemVerilog solution rolls
Cadence Design Systems has released an open source SystemVerilog solution to help users include Synopsys Inc.'s Verification Methodology Manual verification IP (VMM VIP).
2006-05-11 KPIT Cummins adopts Cadence AMS kit
The Indian arm of Cadence announced that KPIT Cummins has adopted its AMS Methodology Kit to help its analog mixed-signal designers simplify the application of Cadence technology.
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