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2002-11-13 Using source constraints in Lattice devices with ispLEVER software
This application presents the syntax and several examples of the constraints of the ispLEVER software.
2003-12-08 Lattice delivers latest ispLever tool version
Lattice Semiconductor has released the ispLever v3.1, the latest enhanced design tool suite for In-System Programmable FPGA, CPLD and ispGDX device design.
2002-12-06 ispLever starter kit
This application note describes the uses and the contents of the ispLEVER starter kit for ISP CPLDs.
2008-09-12 ispLEVER service pack to enhance designer's creativity
Lattice Semiconductor has released Service Pack 1 for ver 7.1 of its ispLEVER FPGA Design Tool Suite, providing the latest LatticeMico32 embedded open source microprocessor enhancements.
2005-02-18 Web downloadable design tool suite supports new LatticeEC FPGAs
Lattice announced the immediate availability of v4.2 of its web-downloadable ispLEVER-Starter programmable logic design tool suite.
2005-11-10 PLD tool suite gives more control to the designer
Lattice Semiconductor released version 5.1 of its ispLEVER PLD tool suite
2006-05-10 PLD tool gets upgrade
Lattice Semiconductor announced the availability of its ispLEVER 6.0 programmable logic design tool suite.
2004-07-23 Lattice upgrades PLD tool suite
Lattice released a new version of its ispLEVER programmable logic tool suite with support for new device families.
2004-11-17 Lattice upgrades PLD tool suite
The latest release of Lattice's ispLEVER features upgrades to the PLD design suite's performance and functionality.
2002-09-19 Lattice rolls out new version of FPGA, PLD design tool
Lattice Semiconductor Corp. has announced the release of the ispLEVER v2.0 design tool suite, adding support for the company's ispXPGA and ispXPLD product families.
2008-12-17 FPGA design tool suite boosts productivity
Lattice Semiconductor has announced Version 7.2 of their ispLEVER FPGA design tool suite with advanced place-and-route algorithms that are said to deliver higher performance results in as much as 30 percent less time.
2005-06-14 First wave of IP support washes over Lattice's FPGA family
Lattice has released for its recently announced LatticeXP FPGA family the first set of IP modules that address the needs of the consumer, computing and communications markets.
2010-08-18 Upgraded design suite provides Verilog visualization
Lattice Semiconductor releases Version 1.4 of its ispLEVER Classic design tool suite, which now includes Synopsys Synplify Pro with the HDL Analyst feature set and an ispMACH 4000ZE CPLD fitter.
2009-06-10 On-chip memory usage guide for LatticeSC devices
This application note discusses memory usage in the LatticeSC family of devices. It is intended for design engineers as a guide to designing and integrating the EBR-based and PFU-based memories of the LatticeSC device family using Lattice ispLEVER design software.
2009-05-19 LatticeECP3 sysIO usage guide
This application note describes the sysIO standards available and how to implement them using Lattice's ispLEVER design software.
2009-05-20 LatticeECP3 memory usage guide
This technical application note discusses memory usage for the LatticeECP3 family of FPGA devices. It is intended to be used by design engineers as a guide to integrating the Embedded Block RAM (EBR)- and PFU-based memories for this device family in ispLEVER.
2008-08-29 Design tools support new ultralow power CPLDs
Lattice Semiconductor has released the ispLEVER Classic ver 1.2 design tool suites that will support all its SPLD, CPLD and select FPGA families.
2009-05-22 Power consumption and management for LatticeECP3 devices
This application note provides information on power supply considerations and the power calculations that the Power Calculator tool provides. Also included are some guidelines to reduce power consumption.
2007-09-03 Low-cost FPGAs offer high-speed Serdes
Lattice Semiconductor Corp. has announced lower price points for the industry's first low-cost FPGAs to offer high-speed embedded Serdes I/O.
2006-11-06 Lattice unrolls PCIe cores for its 90nm FPGAs
Lattice Semiconductor has added to its ispLeverCORE portfolio PCIe IP cores that are optimized for its 90nm LatticeECP2M and LatticeSCM FPGAs.
2003-02-17 Lattice PLD touts speed, size
Lattice Semiconductor's ispGAL22V10A family of ISP simple PLDs operate up to 455MHz with 2.3ns pin-to-pin delay and <300mW standby power.
2007-03-16 Lattice offers 533Mbps DDR2 SDRAM controller IP
Lattice Semiconductor offers the highest possible data rate for a low-cost FPGA with the introduction of the industry's first 533Mbps DDR2 SDRAM controller IP core.
2004-02-09 Lattice CPLD requires 13?A standby power
Lattice Semiconductor Corp. has released the final member of its ispMACH 4000Z family.
2009-01-23 IP core enables next-gen 40Gbit/s systems
Lattice Semiconductor has announced the availability of its 40Gbit/s Serdes framer interface, Level 5 (SFI5) IP core, which uses 17 Serdes channels in the LatticeSC/M devices, including the Lattice SFI5 soft IP core, and enables flexible and high-performance, next-generation 40Gbit/s systems.
2010-08-12 FPGA synthesis deal continues for Lattice, Synopsis
EDA and IP vendor Synopsys Inc. and programmable logic supplier Lattice Semiconductor Corp. announced Tuesday (Aug. 10) a multi-year extension to the OEM agreement that enables Lattice to offer Synopsys' Synplify FPGA synthesis tools to customers.
2005-06-15 Enhanced tool set reconfigures FPGAs while system operates
Programming software supporting TransFR technology, which allows designers to reconfigure LatticeXP nonvolatile FPGAs in the field without interrupting system operation, is available at no charge from Lattice Semiconductor.
2010-07-07 Design software delivers low-power, low-cost FPGAs
The Lattice Diamond FPGA Version 1.0 design software provides as set of tools and a modern user interface to enable designers to more quickly target low power, cost sensitive FPGA applications.
2008-12-15 CPLDs boast 36 percent smaller footprint
Lattice Semiconductor Corp. has announced two new, small-footprint packages for their ispMACH 4000ZE CPLDs. The new space-saving packages enable designers to use these ispMACH 4000ZE devices in a board space that is 36 percent smaller than previously possible.
2006-05-17 Aldec simulators validated for Lattice devices
Aldec announced that Lattice Semiconductor has validated Aldec's Riviera and Active-HDL simulators for use with Lattice devices.
2009-02-26 65nm FPGAs, clock ICs defy downturn
Seeking to grab share in a down market, Lattice has introduced its first 65nm FPGAs in the market and has expanded its family of differential clock distribution ICs. It also announced the availability of 15 new reference designs and a new development kit for its MachXO PLD family.
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