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2010-06-08 Tools offer shared database for design, verification
From Jasper Design Automation come improved versions of the ActiveDesign and JasperGold tools with capabilities that bridge the divide between chip design and verification by sharing common database.
2003-07-03 PLX, Jasper partner on formal verification solution
PLX Technology Inc. and Jasper Design Automation have collaborated to bring formal verification to PLX chips based on PCI Express technology, via the JasperGold formal verification tool.
2004-06-01 Jasper upgrades verification product
Jasper has announced its JasperGold product that enables what the company calls a "provably correct design" methodology
2004-05-06 Jasper upgrades verification product
Jasper Design Automation will announce the latest release of its JasperGold product enabling what the company calls a provably correct design methodology.
2004-07-01 Jasper upgrades verification product
The company has announced the latest JasperGold product enabling what Jasper calls a "provably correct design" methodology
2009-04-30 Jasper finds place in AMD design centers
Jasper Design Automation has signed a long-term agreement with Advanced Micro Devices Inc. to place JasperGold formal verification technology in AMD design centers worldwide.
2014-04-22 Cadence seeks comprehensive verification with Jasper
The combination of Cadence's and Jasper's technologies will result in an inclusive metric-driven verification approach that unites formal and dynamic techniques, accommodating engineers who increasingly adopt formal analysis to complement traditional verification methods
2009-03-02 Verification tools receive upgrades
Jasper Design Automation's ActiveDesign with behavioral indexing is an IC design tool billed as enabling design engineers to capture and preserve intended design behavior as it is being implemented.
2004-10-01 Ventures get capital for a price
There are a lot of startups in EDAprobably too many. If they don't make it, it may sour investors on the sector.
2004-04-06 Synopsys forum updates SystemVerilog support
The message at the Synopsys EDA Interoperability Developer's Forum, convening Thursday (April 1, 2004), is clear; SystemVerilog support is growing.
2004-12-01 Methodology sought for assertion-based verification
Silicon IP providers and creators seek guidelines on how to use assertions effectively, aside from the standard protocols.
2003-06-10 Formal tools won't replace simulation
Formal verification is a valuable adjunct to simulation, but not a replacement for it, according to panelists at the Design Automation Conference
2006-09-01 EDA startup offers free verification planning tool
Verification-focused EDA startup Jasper Design Automation is making available a free tool for tracking the progress of verification plans.
2004-03-04 EDA CEOs predict growth, cite cost concerns
As the semiconductor business continues a slow recovery, the cost of keeping up with Moore's Law is a foremost issue on the minds of EDA customers, said EDA CEOs attending the EDA Consortium forecast panel in February 26, 2004.
2013-01-02 Apply formal methods to power-aware verification
Read about an apps approach for implementing formal methods to power-aware verification.
2007-08-01 'Work smart' mantra mines innovation
It's no secret that demands on engineers have gotten tougher, and symptomatic of pressures on the design community is an upsurge of "embattled engineers." Jasper Design Automation CEO Kathryn Kranen tells us why the "work smarter" approach drives productivity and innovation as opposed to "work harder."
2010-12-17 Proof kits enable faster, accurate SoC verification
Jasper Intelligent Proof Kits encapsulate critical behaviors for popular protocols such as ARM’s AMBA, allowing users to quickly configure designs to the standard or adapt them to their own custom configuration. These kits are optimized for high-level verification with Jasper’s ActiveDesign and JasperGold formal verification
2010-07-30 Proof kit verifies DFI specification
Jasper Design Automation Inc. has released proof kits for the DFI (DDR-PHY) specification. The kits are written in System Verilog.
2005-06-14 Emerging DFM, verification technologies most exciting, CTOs say
Emerging technologies for design for manufacturing (DFM) and verification are the most exciting developments in the design realm, concluded a panel of chief technology officers convened here Monday (June 13) at the Design Automation Conference (DAC
2014-07-21 The semiconductor future according to tech bigwigs, Part 2
This instalment talks about bringing forth the next Golden Age of semiconductors, which requires increased collaboration and cooperation across different disciplines.
2007-07-30 Nokia, ARM among companies in Accellera board
EDA standards organization Accellera has elected 14 Corporate-Member companies to its Board of Directors for the 2007-2008 membership year, among which are Nokia and ARM.
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