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2002-02-19 Xyron offers fresh approach to solve processor latency
Startup IP house Xyron Semiconductor will describe a technology that uses SRAM bits to take care of some of the more mundane tasks that tend to slow down a processor's performance.
2009-11-30 USB audio kit achieves sub-3ms roundtrip latency
XMOS USB audio 2.0 ref design's asynchronous mode is a vital ingredient in the reduction of digital audio jitter which results in superior sound reproduction.
2005-11-09 TI ADC delivers 23.7kSPS channel cycle rate, 42?s latency
Texas Instruments announced a 16-channel, 24-bit ADC which promises the fastest channel cycle rate and lowest latency in its class
2010-01-19 SAR ADC achieves 94dB SNR with no cycle latency
The device offers a temperature-compensated internal reference with a production-tested 0.1 percent initial accuracy and 20ppm/C.
2002-06-16 Samsung unleashes low-latency 'network DRAM'
After a run of unexplained obliqueness about its low-latency DRAMs, Samsung has officially rolled out its "network DRAM," based on licensed IP developed for fast-cycle RAMs by Fujitsu and Toshiba.
2010-07-13 RLDRAM 3 boasts low latency, increased density
Micron Technology Inc.'s third-generation reduced latency DRAM (RLDRAM 3) will be available for sampling in 1H 11.
2005-10-20 New FB-DIMM features low size, latency and power consumption
The IN581AMB fully-buffered DIMM from Inphi is said to be the first device that includes an interface between the high-speed serial interface and DDR2 SDRAM and is fully compliant with the JEDEC AMB specs.
2008-01-16 Managing latency in video encoding, decoding
In applications where there is a closed feedback loop, latency is the most crucial aspect of the system, as it determines whether the system will be stable or not. Keeping the latency of a video codec as minimal as possible is the proper approach for such systems. In many such applications, latency measured in sub-10ms is crucial.
2005-08-01 Low-latency interconnect delivers value
HyperTransport technology is well-positioned for continued growth over the next five to 10 years.
2008-04-23 Low-latency DDR2 SO-DIMM targets notebook market
Kingston Technology announced it is first to offer high-performance, low-latency 667MHz DDR2 SO-DIMM notebook memory to the global market.
2008-12-18 Low latency driver to access external EEPROM using PIC18 family devices
This application note is developed based on low latency design. It provides an algorithm, which is designed to use the SPI/I&3178;C interrupts, to achieve the required communication and enable optimum processor usage.
2004-07-09 Linear ADC features no latency Delta-Sigma architecture
Linear Tech's new low cost 16-bit ADC has a proprietary No Latency Delta-Sigma architecture that allows single-cycle settling time.
2005-02-16 Latency analysis of major chip-to-chip interconnects
Compare and contrast the latency experienced by transactions carried over several of the leading chip-to-chip interconnect standards.
2002-02-12 Infineon samples low-latency DRAMs aimed at networking
Signaling its readiness to fight for the networking market, Infineon Technologies AG said it would start sampling its flavor of low-latency DRAM chips Monday (Feb. 11).
2001-05-03 Improved context save/restore performance and interrupt latency for ISRs written in C
This application note shows both assembly language code and C code examples to optimize performance of the TMS320C2x, TMS320C5x, TMS320C3x and TMS320C4x DSP families.
2011-08-12 Haptic controller chips offer low latency
HiWave Technologies' HIHS9002 is a haptics controller integrated circuit designed for use with the company's haptic exciters to deliver real-time touch feedback.
2014-02-14 Google bets high on lower latency for cloud service
A Google fellow told attendees at the International Solid-State Circuits Conference that data center chips need lower latencies to keep up with the increase in volume of managed data.
2010-07-29 FPGAs support reduced-latency DRAM
Altera Corp.' reveals its Stratix V family of FPGAs features a memory architecture that supports Micron Technology's next-generation reduced-latency DRAM.
2013-06-14 FPGA-accelerated platform boasts 2.4?s latency
Based on the Accelise XP5S620LP FPGA network interface card and running Enyx's FPGA trading application, the platform features real-time market data acquisition over 10Gb Ethernet.
2007-10-03 Algorithm doubles memory at minimum latency
Dubbed Crames, for Compressed RAM for Embedded Systems, the memory doubler algorithm developed by researchers from Northwestern University and NEC Laboratories partitions existing RAM into a solid-state disk that has two-time compression with minimal latency.
2013-11-26 Advantages of low latency networks
There are a number of players carving out a niche with low latency, high throughput networks and networked devices.
2011-12-05 Wireless module delivers up to 24dBM
The LT1110 900MHz from Laird Technologies claims to offer more than 40 times the output power of the current low power LT1110.
2003-07-08 WEDC SSRAMs reduce active memory device count
White Electronic Designs Corp. has expanded their NBL SSRAM portfolio with the release of the W2Z1M72SJ35BC and W2Z512K72SJ35BC devices.
2002-10-21 WEDC introduce 72Mb NoBL SSRAM
White Electronics Designs Corp. has released what it claims to be the industry's first 72Mb No Bus Latency SSRAM.
2010-12-14 Use RLDRAM II memory interface for FPGA
Learn how to use a Virtex-5 device to interface to Common I/ Double Data Rate Reduced Latency DRAM devices.
2004-05-10 UMC, AMIC team up in 90nm SRAM production
UMC and AMIC Technology Corp. announced that they have produced AMIC's high-speed Zero Bus Latency (ZeBL) SRAM using UMC's 90nm process.
2005-01-03 Timing is everything for VoIP success
The only way for VoIP to succeed is to have the right timing--not market timing, but synchronized timing.
2007-03-12 Synthesizable CIO DDR RLDRAM II controller for Virtex-4 FPGAs
This application note describes how to use a Virtex-4 device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design targets two CIO DDR RLDRAM II devices at a clock rate of 200/235MHz with data transfers at 400/470Mbps per pin.
2012-08-17 Overcoming embedded memory bottleneck (Part 1)
Learn about the concept of algorithmic memory and the benefits of memory operations per second (MOPS) as a metric.
2001-03-26 NoBL: The fast SRAM architecture
This application note introduces Cypress Semiconductor's revolutionary NoBL (No Bus Latency) SRAM architecture for high-performance PCs, workstations, communication equipment and network applications.
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