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2008-03-17 Succeed at 65nm design
A true DFM-aware environment accounts for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library, continues through implementation, analysis and optimization, and ends with sign-off verification.
2005-10-11 Design, manufacturing worlds collide at Bacus
If there was a shred of doubt remaining about the magnitude at which IC design and manufacturing convergence is taking place, it was laid to rest last week (Oct. 3-7) at the 25th annual Bacus Photomask Technology symposium in Monterey, Calif
2011-02-03 Implementation platform addresses Gigascale design
Synopsys Inc. releases the 2010.12 Galaxy Implementation Platform that addresses the scalability, convergence and throughput needs of gigascale IC design
2005-03-30 Concurrent' IC design suite rolls
Synopsys rolled out IC Compiler, which concurrently runs physical synthesis, clock tree synthesis, placement, routing, yield optimization and signoff correlation.
2006-07-11 Aprio, Pyxis collaborate on lithography-aware DFM router
Aprio and Pyxis announced the integration of Aprio's Halo-Quest and associated DFM View into the DFM-routing technology from Pyxis.
2006-08-04 IC implementation device targets 65nm/45nm designs
Sierra Design Automation said its Olympus-SoC is targeted for high-end customers who are designing at 65nm and below processes
2005-07-08 Magma provides further details about IBM licensing agreement
Magma Design Automation Inc. has released further details about the physical synthesis and routing technology that it has licensed from IBM Corp
2015-11-27 Place and route sol'n passes Samsung's 10nm qualification
Synopsys announced that its IC Compiler II has been qualified for Samsung Foundry's latest 10nm process, promising significant improvement in throughput and designer productivity.
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