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2007-03-16 CPF-compliant tools aim for low power
Cadence Design Systems Inc. has added the Common Power Format to its existing logic design, verification and implementation tools.
2003-09-10 Xilinx upgrades ISE FPGA design suite
Xilinx Inc. has improved clock performance, software run-time and area utilization in its Integrated Software Environment FPGA design suite
2007-02-05 Xilinx upgrades free ISE Webpack design suite
Xilinx has announced the immediate availability of the ISE WebPACK 9.1i release, the latest version of the company's free downloadable programmable logic design suite
2006-11-06 Xilinx unveils new design solution for Virtex-5 LXT
Xilinx announced the availability of a complete logic design solution including an update to its ISE design tools for their newest Virtex-5 LXT Platform FPGAs.
2006-07-07 Xilinx unveils design tools for 65nm Virtex-5 FPGAs
Xilinx has announced the latest release of its design solution, the 8.2i ISE tool suite, now supporting the company's newest line of 65nm Virtex-5 domain-optimized FPGAs
2006-01-12 Xilinx tool supports embedded, DSP, real-time debug design flows
Xilinx announced the availability of the ISE WebPACK 8.1i programmable logic design tool, which includes all the features of ISE Foundation with full support for embedded, DSP and real-time debug design flows
2007-01-18 Xilinx ISE upgrade shortens FPGA design cycles
Xilinx' ISE 9.1i design suite is optimized to meet today's leading design challenges: timing closure, productivity and power
2008-03-26 Xilinx design tools suit logic, embedded, DSP
Xilinx has introduced its ISE Design Suite 10.1, a single unified release providing FPGA logic, embedded and DSP designers with immediate access to the company's entire line of design tools with full interoperability.
2006-06-29 Xilinx delivers design solution for 65nm FPGAs
Xilinx has released the 8.2i Integrated Software Environment (ISE) design solution supporting the company's 65nm Virtex-5 FPGAs
2005-02-18 Web downloadable design tool suite supports new LatticeEC FPGAs
Lattice announced the immediate availability of v4.2 of its web-downloadable ispLEVER-Starter programmable logic design tool suite
2015-01-07 Using sub-threshold techniques for IC design
The use of sub-threshold techniques can be a powerful way to create circuits that consume dramatically less energy than those built using standard design practices
2009-01-22 Synthesis tools' new versions promise better performance
Synfora Inc. has announced new versions of their PICO Extreme and PICO Extreme FPGA algorithmic synthesis design tools that will achieve higher performance and smaller area than the previous generation of the tools
2003-09-16 SVP is key technology for nanometer IC design
Examine the importance of chip-level architectural issues and the need for physical hierarchy for multi-million gate nanometer SoC design
2008-03-17 Succeed at 65nm design
A true DFM-aware environment accounts for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library, continues through implementation, analysis and optimization, and ends with sign-off verification.
2007-02-01 Startup weaves new foundation for chip design
Fabbrix claims it can provide the regular circuit patterns or 'fabrics' needed by manufacturable designs at 65nm and belowwithout area, performance or power penalties.
2004-09-16 Start thinking out of known 'design box
Package is not simple anymore: IC and package have become a whole and must be treated as such.
2008-12-11 Software tool provides design support for FPGAs
Actel Corp. has announced the availability of Libero Integrated Design Environment (IDE) ver 8.5. This suite of software design tools extends support for the recently announced nano versions of Actel's IGLOO and ProASIC3 FPGAs
2011-01-20 SoC design solution optimized for HKMG tech
Synopsys Inc. announced that it is delivering a low-power, high-performance SoC design solution optimized for the Common Platform alliance (CPA) 28nm high-k metal gate (HKMG) technology
2003-09-16 Register-transfer level design handoff is ready
Shrinking process nodes and tightened purse strings have made the venerable "gate-level design sign-off" unacceptable
2008-10-01 Reap the rewards of package-aware design
Chip designers must consider package routability, power delivery and I/O behavior during the initial I/O planning process. To do so, they should combine package-aware I/O planning with automated floor-plan synthesis, which can be very cost-effective for the chip floor plan and the package layout.
2009-03-11 R3Logic to advance 3D design flow R&D
R3Logic announced that it has created a new R&D center in Grenoble, France to develop and enhance its design tools for 3D heterogeneous system and system-in-package design.
2012-05-16 Quick fix for pesky FPGA design errors
Know the significance of hierarchical design and fast error resolution in achieving a working design with fewer design iterations
2005-03-16 PC-based tools lower barrier to MEMS
Take a closer look at how low-cost PC-based tools can help hurdle the challenges in MEMS design
2004-03-09 Panel debates viability of ESL tools market
As IC designs become larger and more complex, there is a growing need for electronic system level (ESL) design tools
2007-03-02 Mentor, MathStar to develop FPOA design tools
Programmable logic vendor MathStar Inc. has teamed with EDA vendor Mentor Graphics Corp. to develop design tools for the MathStar's field programmable object array (FPOA) devices.
2006-05-08 MathStar announces latest FPOA design tool
MathStar Inc. announced Version 2.0 of the FPOA Design Tools and projected shipment dates for its Field Programmable Object Array device
2003-04-25 LSI Logic, Synplicity to co-develop LSI platform tool
LSI Logic Corp. and Synplicity Inc. have entered into an agreement to provide an optimized physical synthesis tool for LSI Logic's RapidChip customers
2004-05-14 LSI Logic SCSI controller uses Fusion-MPT architecture
LSI Logic has announced that it is now shipping full production volumes of its LSI53C1030T Ultra320 SCSI controller
2005-04-12 Intel's Singer calls for 'platform-oriented' tools
Calling on the EDA industry to broaden its scope, Intel executive Gadi Singer cited the need for tools that support complete "platforms," including multiple chips and software, in a keynote speech at the Electronic Design Processes (EDP
2006-12-22 Indian design industry in transition
India has become a hub for VLSI design but cannot remain competitive solely on the basis of cost and current engineering skill sets, a report warns
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