Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > loop analysis

loop analysis Search results

?
?
total search173 articles
2000-04-19 Switching power supply control loop design
A simplified approach to feedback control loop analysis is presented in this application note. It starts with a general overview of various parameters affecting performance in a switching power system.
2014-10-28 Practical feedback loop analysis for boost converter
The boost converter belongs to the family of indirect energy transfer converters. This application note describes how to select the placement of poles and zeros with several rules.
2003-12-26 Statistical static timing analysis ensures IC performance
Static timing analysis is one of the pilings upon which the whole edifice of modern IC design has been erected
2008-11-12 Stability analysis in multiple loop systems
This paper capitalizes on the Ref. work and explores different ways to apply the technique to power converters featuring multiple feedback paths.
2013-12-11 Securing open source web apps with static analysis
Find out how static analysis can be used to find and eliminate coding errors
2010-05-21 Opinion: Custom IC design needs variation analysis
Incorporating optimal sampling and design-specific corner methods into variation-aware custom IC design can avoid costly over-margining or under-designing, and avoid delaying project schedules.
2005-06-06 Injection transformers for closed-loop dc/dc converter network analysis
This app note discusses current transformer as a voltage transformer
2013-01-09 Improve requirements analysis to eliminate defects
Investment in requirements management, equivalent to that made for design and coding, is needed to ensure a strong foundation on which to build a successful project.
2015-04-28 Exploring the failure analysis process
Determining the root cause of electronic system failures requires a disciplined and systematic analytical process, along with sophisticated tools for testing and visualizing the behaviours of sample devices.
2002-07-22 Electroglas to distribute Applied Precision analysis tools
Electroglas and Applied Precision have into entered a partnership wherein Electroglas will distribute the waferWoRx system throughout North America, Japan, South Korea and parts of Europe.
2006-12-04 Clear Shape offers electrical DFM analysis solution
Clear Shape Technologies has announced OutPerform, said to be the first complete and silicon-correlated electrical DFM analysis and optimization product to enable designers using sub-90nm processes to control the impact of lithography, mask, etch, RET, OPC and CMP effects on their chip parameters
2010-12-17 Bi-directional integrated solution provides efficient loop for composites
Ansys and Vistagy integrate Ansys 13.0 Composite PrepPost and FiberSIM 2010 to deliver quicker, more accurate composites design and analysis. FiberSIM’s Analysis Interface allows optimization of parts, assemblies and structures more efficiently
2008-12-01 Analyzing stability in multiple loop systems
Measuring the frequency response of a multiloop switch-mode power supply can be a real challenge, especially when all the regulation circuitry is kept on the secondary side.
2008-09-03 Agilent touts free PLL analysis software
From Agilent Technologies Inc. comes advanced software for making precise PLL measurements, also called jitter transfer measurements.
2007-01-30 Agilent intros new digital communications analysis tools
Agilent Technologies has introduced a phase noise application software and new options for the digital communications analyzer.
2003-09-19 An Analysis and performance evaluation of a passive filter design technique for charge pump PLL's
This application note investigates the design of passive loop filters for frequency synthesizers using a Phase-Frequency Detector and a current switch charge pump
2005-06-21 A quasi-resonant SPICE model eases feedback Loop designs
This app note shows how a simple large-signal averaged SPICE model can be derived and used to ease the design work during stability analysis
2002-05-01 Single-ended line probing for DSL mass deployment
This technical paper presents the single-ended line probing (SELP), a chip-based design technology that allows the determination of loop characteristics without the need for service providers to perform truck rolls (sending out technicians) to the customers
2002-09-20 A Colpitts VCO for wideband (0.95GHz to 2.15GHz) set-top TV tuner applications
This application note describes the design of a broadband Colpitts VCO that incorporates the SMV1265-011 varactor diode.
2015-11-12 Teledyne LeCroy intros packet capture, inspection system
The Hammerhead for SierraNet Protocol Analysis systems is a dedicated, line-rate protocol analyser that comes with the Wireshark network packet capture application
2014-11-04 Ripple injection methods for hysteretic controllers
In this application note, we highlight the implications of ripple injection techniques, aimed at minimising output ripple voltage, on the transient response of a supply.
2004-12-01 On-chip VCOs can be digitally tuned
One common approach to designing VCOs in CMOS is to build a ring oscillator using a cascaded set of inverters that feeds back into itself.
2015-03-06 Multi-core concurrency: Opportunities and hurdles
In this article, we provide a basic outline of the principles of concurrency, a fundamental mechanism by which multi-core systems manage and coordinate multiple tasks in parallel to achieve higher performance.
2013-08-07 Memory-oriented optimisation techniques (Part 1)
This series examines how to overcome system performance bottlenecks with memory-oriented programming and compiler techniques. Part 1 focuses on loop transformations and a variety of global-, cache-, and scratchpad-oriented optimisations
2012-10-03 Guarding against side-channel attacks (Part 1)
The first installment of this series provides a brief introduction to side-channel analysis, including timing analysis, as well as simple and differential power analysis
2006-05-24 Free PLL design tool debuts with PLL hardware
ADI is rolling out a new generation of its existing ADIsimPLL phased-locked loop circuit design and evaluation tool, as well as two new PLL synthesizers
2005-01-27 Blue Pearl releases RTL optimizer
Blue Pearl Software has announced the release of its first product, Indigo RTL Analysis, for rapid functional closure
2005-07-01 Analog EDA firm tackles PLL noise
Berkeley's PLL noise analyzer promises to shrink time-to-volume for discrete analog/RF chips and SoCs containing analog blocks.
2014-01-21 Advantages of hierarchical flow for SoC design
Learn why it is critical to minimize lengthy problem detection and fix issues as early as possible using a comprehensive hierarchical SoC methodology.
2011-11-17 Address challenges in 40G/100G SerDes design, implementation
Read about the various aspects of SerDes design such as transmit/receive portions.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top