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2007-01-18 Xilinx ISE upgrade shortens FPGA design cycles
Xilinx' ISE 9.1i design suite is optimized to meet today's leading design challenges: timing closure, productivity and power
2008-09-01 Winning the power challenge
Optimizing power consumption in SoCs, DSPs and MCUs has provided good results, but even more can be gained in a joint effort between ICs and the teams that design them. The Texas Instruments article addresses some solutions to today's growing power issues
2009-02-13 What's in store for P1801 (Unified Power Format
A common industry standard for low power design and verification will satisfy what customers have needed all along.
2005-09-14 Vitesse, Apogee Photonics partner on transceiver reference design
Vitesse Semiconductor Corp. and Apogee Photonics recently announced a joint reference design that extends 10Gbps transceiver performance to an industrial temperature range
2007-01-25 Virage Logic joins Low Power Coalition
Virage Logic has joined Silicon Integration Initiative's Low Power Coalition, a unified effort that aims to create a common format for low-power design, implementation and verification.
2008-05-14 VeriSilicon signs up with Power Forward Initiative
VeriSilicon has joined the Power Forward Initiative and plans to offer a CPF-based design solution for its ASIC customers
2008-02-12 USB IP saves power, simplifies connection
Synopsys has expanded it DesignWare USB IP product line with support for the USB 2.0 Link Power Management and High Speed Inter-Chip standards
2007-04-20 UMC joins Power Forward Initiative
Semiconductor foundry UMC is the newest member of the Power Forward Initiative, an alliance of over 20 companies that aims to advance the adoption of the Common Power Format standard for low power design.
2008-06-11 Ultralow-power FPGA aims to break industry records
The folks at SiliconBlue have just announced a revolutionary new class of single-chip, ultralow-power FPGA devices, that they say set a new industry standard for price, power, and space along with unprecedented ASIC-like logic capacity for battery-powered, handheld consumer applications
2004-01-21 Two IP vendors pave the road to low power
The push for low-power ICs in advanced processes has produced little consensus beyond the notion that no single fix will do
2005-06-13 TSMC releases reference design flow for 65nm processes
Taiwan Semiconductor Mfg Co. Ltd has released version 6.0 of its reference flow, the sequence of EDA tools that the world's largest foundry recommends for its 65nm manufacturing processes.
2007-07-16 TSMC pulls curtains off 45nm design process
Taiwan Semiconductor Manufacturing Co. Ltd unveiled its latest and most ambitious design methodology for IC production at the challenging 45nm node
2005-01-26 Toshiba obtains power-efficient design using Synopsys Galaxy
Toshiba Corp. has achieved a 40 percent power reduction on its latest 90nm media embedded processor (MeP) system-on-chip (SoC) design using the Synopsys Inc
2007-03-27 The dilemma of two languages in low-power design
EDA users may not like it, but when it comes to low-power design they will probably have to speak two languages: CPF and UPF.
2013-10-17 Synopsys, TSMC team up to offer 16nm design solution
Synopsys collaborated with TSMC to provide support for voltage-dependent design rules in TSMC's 16nm Custom Design Reference Flow
2008-03-18 Synopsys, SMIC tip 90nm reference design flow
Synopsys Inc. and SMIC have released an enhanced 90nm hierarchical, multivoltage RTL-to-GDSII reference design flow that benefits from advanced synthesis, design-for-test and DFM capabilities
2006-09-07 Synopsys, SMIC team on ref design flow 3.0
Synopsys Inc. and Semiconductor Manufacturing International Corp. announced that they have jointly developed and deployed reference design flow 3.0
2007-08-31 Synopsys, SMIC develop low-power sol'n for China mobile TV market
Synopsys and SMIC have partnered to develop a low-power design solution optimized for the mobile TV market in China.
2007-06-20 Synopsys expands power management efforts with ArchPro purchase
Synopsys has acquired ArchPro Design Automation for an undisclosed price, expanding the former's efforts in the power management arena
2006-09-21 Synopsys donates power management tech to Accellera
Synopsys has donated power management technology to Accellera, the EDA organization focused on electronic design automation standards
2007-04-02 Synopsys design platforms support UPF 1.0
Synopsys Inc. has announced a low-power design flow that will implement the Accellera Unified Power Format version 1.0 in its IC verification and implementation products in the second half of 2007.
2007-06-15 ST unveils low-power 45nm CMOS platform
STMicroelectronics unveiled details of its 45nm CMOS design platform for next-generation SoC product development for low-power, wireless and portable consumer applications.
2009-07-31 ST taps GlobalFoundries for 40nm low-power devices
STMicroelectronics and GlobalFoundries have teamed up to develop products based on 40nm low-power (LP) bulk silicon technology
2006-02-20 ST reduced chip power consumption with Synopsys' IC Compiler
Synopsys announced that the IC Compiler was used to successfully tape out the ultra-low-power version of STMicroelectronics' Nomadik multimedia processor
2009-03-18 Solution supports on-chip power management
Cadence Design Systems Inc. has enhanced the Cadence Low-Power Solution to include support for new on-chip power management schemes enabled by the recently ratified Si2 Common Power Format (CPF) Version 1.1.
2015-03-18 Signal/power integrity device targets high-speed PCB design
The HyperLynx SI/PI tool from Mentor Graphics offers tools for pre- and post-layout signal integrity, timing, crosstalk and power integrity analysis to eliminate design re-spins
2006-10-13 Si2 to facilitate standardization of common power format
Cadence and the Silicon Integration Initiative have agreed on Si2 facilitating standardization of the Common Power Format through the IEEE
2007-05-31 Serial ATA PHY core suits low-power designs
Mentor Graphics Corp.'s new SATA PHY IP core, which is targeted for the TSMC 130nm LVOD process, provides a completely integrated solution for both SATA host and device applications running at up to 3Gbps.
2008-06-02 Save power with omniscient code generation
In lowering power consumption, it is important to minimize the number of instructions a CPU must execute to get the job done, so it can spend as much time as possible in the deepest sleep mode available. This is best accomplished by using a compiler with omniscient code generation technology
2008-09-15 Samsung, Intrinsity join forces on low-power processors
Intrinsity Inc. and the system LSI division of Samsung Electronics Co. Ltd have partnered to develop high performance, low power processors using the Intrinsity Fast14 technology
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