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2004-07-20	Wirebond woes reported for advanced low-k die Problems in wirebonding to dice that use a particular low-k dielectric material in the interconnect stack were reported in a technical paper given Wednesday (July 14, 2004) at the Semi Technology Forum within the Semicon West exhibition.
2002-04-18	UMC tunes low-k material to produce Trident graphics chip United Microelectronics Corp. is seeing some return on its strategy to increase business among graphics chip suppliers while at the same time showing progress in its use of a low-k dielectric insulating material for copper interconnects.
2004-09-21	TSMC claims lead in 0.13-micron, low-k production Taiwan Semiconductor Mfg Co. Ltd said that it has cumulatively produced and shipped more than one million 8-inch equivalent wafers with circuits made using 0.13?m processing.
2003-08-29	Toshiba to use Applied Materials low-k films Toshiba has selected Applied Materials' Black Diamond and BLOk low-k dielectric films to be used for volume production of its 90nm CMOS4 process.
2004-08-31	Spin-on, low-k dielectrics remain viable The ultimate ultra-low-k material that complies with the future microelectronics industry has not yet been found. The race between spin-on and CVD-deposited materials is still ongoing.
2004-06-23	NEC devises low-k film for 2G 65nm process NEC Corp. announced it has developed a 2G, 65nm process with multilevel copper and low-k dielectric interconnects.
2004-10-26	Mitsubishi touts new low-k material Mitsubishi claims to have developed an insulator material with a lower dielectric constant and increased robustness compared to current materials.
2004-12-01	Japanese companies strengthen low-k materials Mitsubishi says its product is 6x stronger; Zeon claims a 2x hit over current materials.
2013-07-11	Imec demos damage-free cryogenic etching of ultra low-k mat'l By applying very low temperatures during etching, a condensation of etch products in the pores of the low-k material results in a protection of the dielectrics' surface.
2005-06-08	Fujitsu tips new spin-on, low-k for 45nm At the IEEE International Interconnect Technology Conference (IITC) here, the buzz was centered on a paper from Japan's Fujitsu Ltd, which believes that spin-on glass is not dead in the water for low-k dielectric applications
2004-02-12	Cypress-Silects co-develop low-k materials for chip devices Cypress Semiconductor and Silecs have agreed to collaborate on the development and testing of Silecs' novel, non-porous, low-k dielectric materials.
2007-10-24	Collaboration by Elpida, UMC to boost low-k, PRAM Japan's Elpida Memory has formed a joint development program with Taiwan's UMC for copper low-k and PRAM.
2004-05-31	Chipworks claims UMC-made 90nm part lacks low-k process A Canadian semiconductor engineering services company claimed that the L90 manufacturing process from Taiwanese foundry United Microelectronics Corp. used in a Spartan-3 FPGA from Xilinx Inc. does not use a low-k interlayer dielectric, contrary to publicity material.
2004-02-09	ATI commits to low-k for mobile GPU ATI has released its Mobility Radeon 9700 notebook PC graphics processor.
2002-07-09	ASM receives patents for PECVD low-k dielectric technology ASM Int. N.V. has been granted patents no. 6,352,945, 6,383,955 and 6,410,463 by the U.S. Patent & Trademark Office.
2008-03-07	AMD taps low-k dielectrics for 45nm chips Advanced Micro Devices has started shipping samples of its first 45nm processors and is on track to start production in the second half of the year.
2003-04-09	Agere claims first low-k DSP for comms The company has employed TSMC's 130nm low-k process on its designs; claiming it is ready for volume shipments of a DSP aimed at cellular basestations.
2005-12-01	Where the silicon hits the board Amkor's Chris Scanlan talks about the evolution of stacking technology and the road to environmentally friendly packages.
2002-02-13	UMC dropping Dow's SiLK from performance 130nm process After working with Dow Chemical's low-k dielectric film for nearly a year, UMC is preparing to drop Dow's SiLK from its high-performance 130nm process, choosing a path different than that of development partner IBM Corp.
2002-04-15	TSMC exec advocates slower steps between process nodes Taiwan Semiconductor Mfg. Co. Ltd said it aims to deliver its first ICs based on 90nm design rules by the third quarter of this year, about one year ahead of the time frame cited in the industry's International Technology Roadmap for Semiconductors.
2008-02-07	TI bares details of 45nm process TI has revealed that its 45nm process uses strained silicon, immersion lithography and ultra-low k dielectrics to lower power and increase performance compared with its 65nm process, and double the number of chips produced on each 45nm silicon wafer.
2003-02-07	Shipley opens R&D facility for microelectronic materials Shipley Co. L.L.C. has opened its Advanced Technology Center in Marlborough, Massachusetts.
2005-07-18	New dry strip system from Mattson Mattson introduced its new Aspen III eHighlands dry strip system designed for critical front-end-of-line (FEOL) and back-end-of-line (BEOL) process applications, including photoresist strip over low-k materials.
2006-06-08	Matsushita process enables air-gap interconnects for ICs Matsushita Electric described what the company claims to be a viable replacement for conventional low-k films.
2007-10-18	Industrial affiliation program tackles 32nm IC packaging Two research centers are inviting industry partners to participate in an advanced research program on next-generation flip-chip and substrate technologies.
2004-06-14	IC power strategies sought as complexity grows Power management is getting tougher as more aggressive processes are employed in chip design, adding to the complexity problems that threaten to overwhelm the EDA industry, a panel at the Design Automation Conference here concluded.
2010-08-19	Air gaps move up from chip- to board-level The Semiconductor Research Corp. sees air-gap interconnections migrating from the chip-level, to the PCB-level.
2003-07-07	TSMC, Amkor partner on flip-chip packaging Amkor Technology has developed and qualified wirebond and flip-chip packaging for devices manufactured on TSMC's advanced low-k process technologies.
2011-01-24	Samsung launches 20nm technology Designed for logic and foundry applications, Samsung's 20nm process features bulk CMOS technology, 12 metal layers, copper interconnects, ultra low-k, stressors and a high-k/metal-gate scheme.
2003-04-21	NEC to use Applied Materials dielectric films NEC Electronics has selected Applied Materials Inc.'s Black Diamond and BLOk (Barrier low-k) dielectric films for its UX6 chips.