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2010-09-22 Reality? project characterizes ARM926 for inherent variability at 32nm
An IMEC-led project, called “Reality?, has conducted a characterization of an ARM926 core for the statistical variability that is inherent at the 32nm manufacturing process node. The research project, set up in 2008, has cost about $5.8 million.
2012-10-23 TCAD eases FinFET design and variability analysis
FinFET is the first fundamental change in transistor architecture since the time MOSFET replaced bipolar transistor as the transistor of choice for logic applications.
2008-12-25 Studies address process variability issues
CMOS device process variability remains one of the most acute problems facing the semiconductor world, particularly at the 45nm node and beyond, according to presenters at the International Electron Devices Meeting (IEDM
2006-06-01 Startup enables IC variability characterization
In a bid to enable silicon fabs to provide statistical parametric characterization, Stratosphere Solutions Inc. recently introduced intellectual property that inserts test structures in silicon wafers.
2006-06-28 Routing solution speeds design to manufacturing
The Cadence Precision Router speeds design and manufacturing convergence for advanced mixed-signal, analog and custom digital designs
2009-03-24 Process variability gets a second chance
Mentor Graphics Corp. has a new message: process variability is not all bad. In fact, it could be considered a competitive advantage if properly dealt with, according to executives at the firm
2005-12-01 Manufacturing moves into design flow
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2012-06-08 Intel finFETs show variability, need SOI for scaling
GSS has concluded that Intel may need to turn to SOI wafers to scale its FinFETs below 22nm, which may have implications for foundries that are yet to introduce FinFET technology into their chip manufacturing processes
2006-06-01 Hope seen for taming IC process variability at 65nm
Presentations at the recent International Symposium on Physical Design offered new hope for chip design at 65nm and below, where temperature, voltage and process variations can have a dramatic impact on chip timing, manufacturability and yield.
2010-09-20 Evolution of manufacturing closure for advanced nodes (Part 1
Manufacturing closure has become a key design challenge at smaller technology nodes such as 32nm and 22nm. This article, the first of three parts, discusses the new challenges in manufacturing closure
2006-04-20 EDA tool manages process variability early in design stage
Mentor Graphics announced its Calibre LFD (Litho-Friendly Design) product, which is touted to be the first production proven, EDA tool to address the urgent issue of how to manage process variability in the early stages of design creation
2006-01-11 Mentor tool aims to manage process variability on yield
Mentor Graphics announced the availability of the Calibre OPCverify tool, which aims to address the challenge of managing the impact of "process variability" on yield
2006-10-31 Synopsys unveils DFM tools for 45nm, beyond
Synopsys has unveiled a new family of process-aware DFM products that analyze variability effects at the custom/analog design stage for 45nm and smaller designs
2008-03-17 Succeed at 65nm design
A true DFM-aware environment accounts for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library, continues through implementation, analysis and optimization, and ends with sign-off verification
2005-07-01 The need to design for uncertainty
If there was a message for chip designers from two recent industry conferences, the ISPD and the EDP, it was this: Get used to uncertainty. The era of 'design for variability' is here
2003-12-01 Process tool promises yield optimization
PDF Solutions is expanding into EDA with a tool that claims to improve designs for optimum yield during the physical-synthesis step in the digital IC design process.
2011-01-04 Market trends and the electronics industry
As the cost of IC design advanced nodes increases, companies are also looking at embedded systems to shorten the development cycle and increase the potential for hardware reuse.
2007-03-05 Integrated DFM solutions still lacking
According to a Charted Semi exec, EDA has done a great job of raising awareness of DFM issues, but integrated DFM solutions remain scarce.
2006-10-18 IC design tool touts process-aware DFM
Synopsys two "process-aware" tools that help custom- and analog-IC designers analyze the impact of transistor variability on circuit layouts
2012-12-04 Globalfoundries ready to roll out FinFET wafers
The chip making giant's first multi-project wafer runs, which are aimed at customers testing their 14nm FinFET manufacturing process technology, could start as soon as the first quarter of 2013
2006-03-16 ESL design tools come up short
ESL and DFM tools need to pack far more capabilities than they do today if they are to represent the EDA industry's best opportunities for growth.
2007-03-16 Electrical DFM promises gains in parametric yield
Design techniques are under greater pressure to provide equivalent scaling to enable the semiconductor road map to continue in a cost-effective way.
2007-10-01 Drive parametric yields higher at 65nm, beyond
The need to characterize and model intrinsic variability in a production-worthy process will intensify and represent a new imperative for improving yield in 65nm process technologies and beyond. A PAM platform methodology can foster a collaborative environment between design and manufacturing, a condition key to driving parametric yields higher.
2007-03-16 DFM demands holistic approach
The infrastructure required to make trade-offs among the different techniques and determine the optimal approach should be one where the actual software takes into account the implications of other DFM issues. The idea is to create a holistic approach to DFM for the design and analysis flow.
2009-07-31 DAC panel revisits DFM debate
Panelist revived the debate on design for manufacturing, with one executing calling it a 'band-aid with diminishing returns
2007-01-19 Clear Shape, STARC to develop DFM flow
Clear Shape Technologies Inc. announced a partnership with STARC to jointly develop, validate and deploy a variability-aware DFM flow
2008-03-17 Bring DFM/DFY into the routing engine
In reality, DFM/DFY tools need to use a mixture of rules- and model-based techniques as appropriate. The solution is to bring DFM/DFY upstream into the design process; to create a design that is correct by construction; and to hand-off a design that is as manufacturing- and yield-friendly as possible
2007-09-17 Avoid design snags with silicon contour predictor
Designers can improve parametric yield and chip performance by accurately determining the impact of systematic variations during design.
2014-07-31 3D-IC: Taking the next steps towards broad adoption
Technology firms are applying manufacturing intelligence across test operations to bring the associated costs in line with required levels of profitability
2006-11-16 'DFM too complex,' experts say
Speakers told the Bacus Photomask Technology Symposium that DFM technology is too complex and suggested the use of standardized layout elements, library cells or an "integrated" DFM methodology.
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