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2005-02-07 Cadence plans restructuring, tips DFM initiative
Buoyed by strong fourth-quarter results, Cadence Design Systems Inc. is going into 2005 with a new organizational structure and a stealth-mode initiative, dubbed Catena, aimed at &quote;manufacturing-aware&quote; design.
2004-11-10 ICCAD keynoter calls for EDA to become more
Design tools need to become power aware, physically aware, manufacturing aware, signal integrity aware and test aware starting at the 90nm node, said Texas Instruments Fellow, Peter Rickert, here Monday (Nov. 8) in his keynote at ICCAD 2004.
2006-02-03 Cadence unveils new silicon-proven full-chip optimization system
Cadence Design Systems announced its new manufacturing-aware chip optimization product Cadence Chip Optimizer, which is a silicon-proven full-chip optimization system.
2006-07-26 TSMC adds support for Blaze DFM optimization software
Taiwan Semiconductor Manufacturing Co. Ltd is adding support for Blaze MO optimization software from Blaze DFM Inc. with both companies supplying evaluation kits.
2004-06-15 Transition to 90nm raising tough design issues
Experts delving into 90nm design and process development explored a crucial question: How will the average design team handle 90nm design?
2006-08-30 Toshiba adopts Cadence solution for 65nm design
Cadence Design Systems announced that Toshiba has adopted Cadence QRC Extraction for its most advanced 65nm design flows.
2006-09-22 Synopsys, Nikon co-develop 45nm solutions
Synopsys and Nikon have tied up to develop and deliver advanced lithography software models and DFM-enabled lithography manufacturing solutions for 45nm and below.
2007-09-04 Qualcomm joins IMEC's 45nm design program
Qualcomm has joined IMEC's technology-aware program and will be collaborating with the research institute on design methodologies for sub-45nm scaling challenges.
2005-09-23 Platform partners integrate design-for-manufacturing
IBM, Chartered Semiconductor Mfg and Samsung Electronics Co. Ltd have entered into an initial set of solutions for their cross-fab, common design-for-manufacturability (DFM) initiative. The multi-faceted effort, which includes participation by electronic design automation (EDA) and DFM tool suppliers, is expected to offer a series of rules, models and utility kits that provide new levels of predictability and control to achieve working silicon faster and yield ramp more efficiently.
2005-12-07 P.A. Semi's 65nm processor developed with Cadence platform
Cadence said its Encounter digital IC design platform has helped P.A. Semi develop its new 65nm multicore PWRficient processor with a successful test-chip tapeout in March 2005.
2005-01-14 OPC tool aims to cut IC manufacturing time
Aprio Technologies will introduce its first product this weeka "reconfigurable" OPC tool suite aimed at manufacturing groups.
2004-12-16 Interconnect variation: Garbage in, out
The transition to copper and 90nm process nodes has raised the specter of increased interconnect process variation.
2003-05-02 EDA, test vendors ponder interoperability at DATE
EDA tool vendors, test companies, and IP providers sat down at the recent DATE conference to discuss how they can better address interoperability issues.
2007-01-19 EDA, IP revenue up 17% in Q3 '06
Worldwide EDA and IP revenue in Q3 of 2006 grew 17 percent over the prior year quarter, according to a report issued by EDAC.
2005-05-27 EDA vendors announce flows for IBM-Chartered 90nm process
IBM and Chartered Semiconductor Mfg added common design support to their jointly developed 90nm process platform.
2006-09-01 EDA app shows variants of IC design
DFM tool provider Aprio Technologies Inc. has developed an application extension, Halo-Quest, designed to fit on top of EDA design and analysis tools, and to generate accurate silicon image representation of IC designs for use within design flows.
2008-12-05 Digital implementation platform promises scalabilities
Cadence Design Systems Inc. rolled out Encounter Digital Implementation System, RTL-to-GDSII configurable digital implementation platform geared toward the 45nm and 32nm nodes.
2005-10-11 DFM delays 90 and 65nm, analyst says
Design for manufacturability (DFM) concerns have slowed the ramp-up of 90nm wafer volumes and will be even more problematic at 65nm, said Handel Jones, CEO of International Business Strategies Inc., at the Fabless Semiconductor Association Expo Thursday (Oct. 6).
2006-09-08 Cadence, SMIC co-develop digital ref flow for 90nm tech
Cadence Design Systems and SMIC announced that they have jointly developed the low-power digital reference flow to support SMIC's advanced 90nm process technology.
2010-01-13 An EDA company's take on 2010 growth sectors
P.V. Srinivas at Mentor Graphics takes you for a spin of crystal ball gazing, predicting growth sectors for 2010 and processes that will feed enabling technologies into electronics products.
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