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memory interface What is a memory interface? Search results

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What is a memory interface?
An external memory interface is a bus protocol for communication from an IC, such as a microprocessor, to an external memory device located on a circuit board. Internal memory interfaces apply to communication with on-chip memory. The asynchronous External Memory Interface (EMIF) is a Texas Instruments IC bus used in their DSPs and digital media SoCs.
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2012-03-16 Xilinx, Micron demo FPGA, RLDRAM 3 memory interoperability
Virtex-7 and Kintex-7 FPGAs come with IO standards and architectural components for optimal interfacing with RLDRAM 3, boosting system performance for high-performance wireless and wired networking systems.
2014-03-12 Xilinx adds DDR4 interface to UltraScale devices
The DDR4 memory interface in UltraScale devices provides over 1Tb/s of memory bandwidth suitable for video imaging and processing, traffic management and high-performance computing.
2008-05-02 Work underway on mobile DRAM interface spec
The Serial Port Memory Technology Working Group has been formed to devise an open standard for a next-generation DRAM interface technology in mobile products.
2008-07-18 Virage new DDR3 interface handles up to 1.6Gbit/s
Virage Logic has broadened its Intelli DDR memory interface product portfolio with the Intelli DDR3 memory interface that operates up to 1.6Gbit/s.
2008-06-19 Using the STR91xFA external memory interface (EMI)
The STR91xFA EMI bus is a very flexible bus and is user programmable. The bus can be configured to interface to different types of memory devices, including SRAM, flash memory, ROM or PSRAM.
2008-05-26 Using the FullFlex dual-port DDR interface
Cypress Semiconductor's FullFlex Dual-Port offers DDR mode to achieve the same data bandwidth of an SDR interface with half of the data pins, or twice the data bandwidth with the same amount of pins
2008-09-10 Using external data memory with PIC24F/24H/dsPIC33F devices
This application note describes the methodology to use the Parallel Master Port (PMP) module to interface with external data memory; either external flash or external RAM
2010-12-14 Use RLDRAM II memory interface for FPGA
Learn how to use a Virtex-5 device to interface to Common I/ Double Data Rate Reduced Latency DRAM devices
2010-12-15 Use QDR II SRAM interface for FPGA
Read about the implementation and timing details of a Quad Data Rate SRAM interface for Virtex-5 devices
2001-05-11 Understanding the TMS320F240 external memory interface
This application note describes the features and operation of the external memory interface of Texas Instruments' TMS320F240 DSP.
2003-10-22 Transmeta microprocessor features HyperTransport interface
Aimed at portable and mainstream notebook computers, the TM8000 Efficeon family microprocessors is based on a silicon microarchitecture.
2006-10-13 Toshiba, Rambus expand memory interface agreement
Toshiba Corp. and Rambus Inc. have expanded their memory-interface licensing agreement.
2001-05-15 TMS320C6000 EMIF to TMS320C6000 host port interface
This application note describes the interface between the host port interface (HPI) and the external memory interface (EMIF) of Texas Instruments' TMS320C6000 DSP.
2001-05-10 Shared memory interface with the TMS320C54x DSP
This application note describes how to share memory (SRAM, FIFO, dual-port RAM) between Texas Instruments' TMS320C54x DSP and Host or other DSP
2008-11-13 Sharc DSPs boost memory capacity
Analog Devices has announced the ADSP-2164x, the fourth-generation of its Sharc floating-point DSPs, offering two times performance boost over earlier Sharc DSP and a 60 percent increase in on-chip memory capacity
2001-06-11 Serial memory interfaces: Trends and options
This application note examines serial memory interface trends and evaluates the three leading interface standards.
2001-06-08 Serial memory interface: The benefits of SPI over I?C and ?Wire
This application note examines serial memory interface trends and evaluates the three leading interface standards that include SPI, I?C and ?Wire.
2006-08-31 SDRAM memory controller targets streaming video apps
Targeting streaming video applications, Microtronix's multiport SDRAM memory controller IP core supports up to 1024 x 768 (true color) 32bit display resolution
2009-01-23 RLDRAM II memory interface for Virtex-5 FPGAs
This application note describes how to use a Virtex-5 device to interface to Common I/O (CIO
2004-05-18 Rambus, Denali to offer memory controller solutions
Rambus Inc. and Denali Software Inc. have revealed plans to jointly provide DDR memory controller design solutions
2011-05-13 Rambus taps startups to explore next-gen memory tech
Keen on developing potential flash and DRAM successors, Rambus is investing in memory technology startups and lending support to universities researching next-generation memory technologies
2007-11-28 Rambus shows alternative way to terabyte memory
Rambus has developed technologies that could enable links to memory chips delivering up to a terabyte per second and could provide a lower-cost alternative to 3D chip stacking
2015-08-19 Rambus goes fabless with DDR4 server memory chipset
Rambus said its new DDR4 RDIMM and LRDIMM chipset make a big difference in server-based memory performance by delivering increased speed, reliability and power efficiency
2011-06-17 Rambus details memory clocking tech
Rambus' new memory clocking technology uses a calibrated feed-forward architecture to achieve extremely fast turn-on and turn-off, simplifying system design and reducing overall system power requirements
2009-04-01 QDR II SRAM interface for Virtex-5 devices
This application note describes the implementation and timing details of a Quad Data Rate (QDR II) SRAM interface for Virtex-5 devices
2007-05-09 New memory interface touts 10x I/O bandwidth increase
HyperLink NAND, a new memory interface, will reportedly increase I/O bandwidth in flash by more than 10x today's conventional devices.
2009-04-17 New JEDEC standard doubles memory interface performance
JEDEC Solid State Technology Association announced the publication of JESD84-A44 MMC ver. 4.4 standard. The new standard offers designers a doubling of the memory interface performance, flexible partition management and improved security options.
2006-04-03 Mobile phone chip interface gets real
MIPI Alliance unveils plans to release interfaces for displays, PHY, audio and power management, and other peripherals in the next two years.
2011-05-06 MIPI, USB 3.0 promoters collaborate on mobile chip interface
Designed for next-gen mobile silicon, the Superspeed Inter-Chip spec unites MIPI Alliance's M-PHY spec with USB 3.0's media access controller and higher layer software.
2004-12-27 Memory interface package woes
Previously, I have addressed the component packaging problems found in FPGAs and perhaps given the impression that other packages were OK.
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