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memory interface What is a memory interface? Search results

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What is a memory interface?
An external memory interface is a bus protocol for communication from an IC, such as a microprocessor, to an external memory device located on a circuit board. Internal memory interfaces apply to communication with on-chip memory. The asynchronous External Memory Interface (EMIF) is a Texas Instruments IC bus used in their DSPs and digital media SoCs.
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2007-10-12 MCU supports emerging car interface standards
NEC Electronics' V850E/CAG4-M automotive MCU extends the V850 32bit MCU family into the high-performance range, with the FlexRay and MediaLB interfaces supporting emerging standards for communication within automotive applications.
2005-06-06 MCU provides large memory space
Holtek's new MCU contains 4K of OTP Program Memory and 192 bytes of General Purpose Data Memory, providing the user with a flexible and large app memory space for more complicated apps with larger data requirements
2008-03-18 MCU integrates SMSC MediaLB interface
Fujitsu Microelectronics Europe has started to implement SMCS's Media Local Bus technology in the latest member of its 32bit MB91460 MCU product series.
2006-04-10 MCU integrates flash memory
Toshiba announced the expansion of its embedded flash MCU product line with the addition of a new 16bit MCU and six new 8bit MCUs.
2006-06-21 MCP memory has 2GB NAND, SD card controller
Toshiba's new MCP memory with 2Gbyte NAND flash memory and SD card interface targets mobile phones.
1999-12-10 MB86930 SPARClite DRAM CONTROL INTERFACE
This application note outlines the design used on the Fujitsu SPARClite Evaluation Board to interface the MB86930 with the DRAM subsystem. The main objective of the paper is to show the simplicity of the external design requirements, while achieving high performance of three CPU cycle page mode access at 40MHz
2013-08-01 Many-core interface identifies chips to OS, software
MCA aims to expedite time to market for new chips and associated software by establishing a standard way to automatically pass hardware details about a many-core processor to low-level software.
2014-09-23 Main memory bootloader for MSP430 MCUs
Read about the implementation of a bootloader that resides in the main memory in an MSP430 microcontroller and uses I2C communication but supports different communication interfaces
2004-07-06 LSI Logic PHY interface supports to 667Mbps
LSI Logic's new PHY interface to QDR-2 SRAM memory enables the next generation of high-end network routers, switches and host bus adapters.
2014-08-27 LPDDR4 spec doubles memory throughput
JEDEC's JESD209-4 implements a two-channel architecture that delivers 16bit per channel, resulting in twice the I/O data rate of LPDDR3 while reducing power required to transmit huge amount of data.
2009-11-17 Low-frequency interface ensures stable communication
Ti offers the first passive low-frequency interface device designed to wirelessly supply an ultralow-power MSP430 MCU with energy to operate even if the optional battery is empty
2009-05-20 LatticeECP3 high-speed I/O interface
This application note describes how to use the capabilities of the LatticeECP3 devices to implement the high-speed generic DDR interface, and the DDR, DDR2 and DDR3 memory interfaces.
2008-08-01 Keeping up with flash memory growth
Hyperstone's flash memory controllers have evolved to multiple product lines, which include the F2/F3 series that zeroes in on the CF card standard, and the S2/S3/S4/S6/S7 series targeting the SD/MMC card standard. Apart from carrying proprietary 32bit RISC processor core, the products feature hardware units such as the ECC, buffer, flash memory and host interface control logic.
2011-03-01 JEDEC releases new flash memory spec
Governing embedded and removable flash memory-based storage, the Universal Flash Standard builds on the e.MMC standard and adds security, performance and power consumption features
2005-02-16 Intersil DCP with non-volatile memory for wiper position
Intersil's new low noise, low power, 256-tap DCP is designed for system applications requiring control, parameter adjustments or signal processing.
2008-08-08 Interfacing the MSP430 with MMC/SD flash memory cards
This application report and the associated source code files demonstrate the implementation of a serial peripheral interface (SPI) between the MSP430F161x MCU and an MMC or SD flash memory card used in SPI mode.
2011-10-12 Interfacing DDR3 memory module with DS34S132
Learn how to interface the DS34S132, a 32-point TDM-over-packet IC, with a DDR3 memory chip.
2009-03-06 Interface design guide for STMicroelectronics Cartesio microprocessor
This technical note provides guidelines for interconnecting the STA2062 dynamic bus controller to two Micron 512Mb Mobile DDR SDRAM devices to achieve a 128MB external dynamic memory without series termination resistors other than clock line parallel terminations
2012-10-20 Interface Bridge SoC boasts 10 interfaces
The MB86E631 from Fujitsu Semiconductor brings together a dual-core ARM Cortex-A9 processor and a host of different interfaces in a single chip.
2013-09-05 Interface bridge IC fuses de-interlacing, video scaling
The T358749XBG integrated video preprocessing functions replace software processing and significantly reduce memory bandwidth and video processing requirements on the host processors
2008-08-12 Interface board built for high-speed data comms
Fujitsu Components America Inc. has introduced an interface board series for its 2-inch, 3-inch and 4-inch 5V thermal printer mechanisms
2004-11-22 Intel StrataFlash memory to Intel IXP42X product line of network processors and Intel IXC1100 control plane processor design guide
This app note covers the interface between Intel StrataFlash memory device, Intel IXP42X network processor and Intel IXC1100 control plane processor.
2006-12-01 Intel StrataFlash embedded memory to Freescale ColdFire MCF5272 design guide
This application note describes the interface between the following Intel StrataFlash embedded memory device and Freescale Coldfire MPC5272 processor and discusses general concepts involved when interfacing the features and control signals of the P30 flash memory device.
2006-12-01 Intel StrataFlash cellular memory to ARM PrimeCell design guide
This application note describes interfacing Intel StrataFlash Cellular Memory to ARM PrimeCell synchronous static memory controller (SSMC) and multi-port memory controller (MPMC) as well as integrated features and control signals for interfacing the M18 flash memory and LPSDRAM to the SSMC and MPMC, respectively
2002-05-22 Innoventions launches DDR memory tester
Innoventions Inc. has launched its 184-pin Ramcheck DDR Adapter to test DDR SDRAMs including PC2700, PC2100, and PC1600 modules, as well as registered and unbuffered DIMMs.
2002-04-30 Infineon security controller provides USB interface
Infineon Technologies AG has announced the release of the SLE66CUX640P USBsec security microcontroller that integrates a USB interface, providing public key cryptography, secure network log-on, and e-commerce transaction authentication for USB-enabled cards and USB dongles
2005-09-02 Infineon defends memory stance
Allaying recent rumors about plans to spin off its memory unit, Infineon Technologies AG defended the business despite a lackluster outllook for the sector
2014-11-24 Improve software through memory-oriented code optimisation
In this instalment, we will explore different software code and compiler optimisation techniques that can be used to boost memory performance in embedded systems
2012-08-09 Improve SoC yields with diagnostic and repair tools for embedded memory
Learn about embedded memory test solutions, including fault detection in very deep submicron technologies, repair at the manufacturing level, as well as diagnosis for process improvement and field repair capabilities
2015-01-09 Identifying memory trends: Issues, standards and specs
Jennie Grosslight, the memory test product manager at Keysight Technologies, revealed what she thinks will be the prevailing memory trends in 2015
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