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What is a memory interface?
An external memory interface is a bus protocol for communication from an IC, such as a microprocessor, to an external memory device located on a circuit board. Internal memory interfaces apply to communication with on-chip memory. The asynchronous External Memory Interface (EMIF) is a Texas Instruments IC bus used in their DSPs and digital media SoCs.
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2007-03-12 Memory interface appnotes overview
This document provides an overview of all Xilinx memory interface application notes that support Virtex series and Spartan series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly.
2004-12-10 Memory interface application notes overview
This app note provides an overview of all Xilinx memory interface application notes that support Virtex series FPGAs.
2014-12-22 Memory access ordering in complex embedded designs
The simple act of loading, storing, and transferring data between processor and memory is much more complex than it used to be. This article focuses on memory accesses, specifically the order in which they happen
2004-07-22 Matsushita selects Rambus interface for TV chips
Matsushita Electric Ind. Co. Ltd, Japan, has signed an agreement with Rambus Inc. to integrate that company's DDR2 interface cell into its next-generation digital television (DTV) chipsets
2002-09-02 LSI Logic DSP integrates 48Kwords of memory
LSI Logic Corp. has announced the availability of the LSI403LP configurable DSP that features a total of 48Kwords of on-chip memory, eliminating the need for external memory
2004-05-03 LSI Logic ASIC offers one of the highest logic, memory content
LSI Logic has disclosed that its RC11Si250 slice offers the highest logic and memory content of all 0.11m Platform ASICs
2009-06-16 LatticeSC/M DDR/DDR2 SDRAM memory interface user's guide
This user's guide discusses a memory interface for a Double-Data-Rate SDRAM (DDR/DDR2 SDRAM) implemented in the LatticeSC and LatticeSCM FPGAs.
2012-04-17 JEDEC focuses on non-volatile memory standardization
Nokia, Micron and Samsung have announced support for the subcommittee known as JC-64.9 that targets wireless data transfers in embedded memory storage and removable memory cards
2010-09-02 IP core enables NVM interface running at 3.12Gbit/s
Arasan Chip Systems Inc. reports that it has developed the ultra high speed (UHS)-II PHY IP core, a memory interface being finalized by the SD Association.
2001-05-01 Interfacing memory to the TMS320C32 DSP
This application note explains the features of Texas Instruments' TMS320C32 DSP enhanced memory interface and gives examples of ways to interface external memory to the TMS320C32.
2003-09-17 Interface deal links Artisan with Denali
Artisan Components Inc. and Denali Software Inc. have teamed to deliver near-turnkey IP for advanced double-data-rate DRAM interfaces on system-level chips.
2004-05-14 Intel StrataFlash wireless memory system (LV18/LV30 SCSP) to ARM Primecell memory interface design guide
This app note describes the interfacing of Intel StrataFlash wireless memory system (LV18/LV30 SCSP) device to Advanced RISC Machines Ltd (ARM) Primecell external memory interface peripherals.
1999-10-01 Improving memory access timing in Z182 applications
This application note demonstrates the calculations of both ROM and RAM access timing, and provide examples of a conventional processor/memory interface design for V.FAST modem with processing speeds approaching 33MHz.
2000-09-08 Improving memory access timing in Z182 applications
This application note demonstrates the calculations of both ROM and RAM access timing, provides examples of a conventional processor/memory interface design, and presents an alternate approach to processor/memory design.
2001-05-14 Implementing shared memory interface with a TMS320C54x DSP
This application note describes how to share memory (SRAM, FIFO, dual-port RAM) between Texas Instruments' TMS320C54x DSP and Host or other DSP
2008-06-09 Implementing DDR2-400 memory interfaces in Spartan-3A FPGAs
High-performance consumer products and their requirement for low-cost, high-bandwidth memory create demand for high-performance DDR2 memory interfaces. Xilinx offers a Memory Interface Generator (MIG) integrated in the CORE Generator software for ultimate design flexibility and ease-of-use.
2007-08-16 Implement the right flash memory interface
Mobile products need flash memory. Implementing the most appropriate interface will increase system performance and reduce the BOM.
2013-01-24 Imec, Cadence team up for DFT solution for 3D memory
Cadence's and imec's solution includes generation of DRAM test control signals in the logic die and inclusion of the DRAM boundary scan registers test access mechanisms of the 3D test architecture.
2003-06-25 ICS offers Yellowstone memory interface clock generators
Rambus Inc. has announced that Integrated Circuit Systems has offered clock generators for the Yellowstone memory interface.
2013-04-04 Hybrid Memory Cube Consortium to focus on faster DRAM
Micron, Samsung, Hynix are among over 100 companies releasing a specification for a 3D DRAM and logic module known as the Hybrid Memory Cube
2005-09-08 How to interface DDR-II SRAMs with Stratix II devices
DDR-II SRAM devices offer enhanced timing margin and flexibility
2005-09-08 How to interface DDR-II SRAMs with Stratix II devices
DDR-II SRAM devices offer enhanced timing margin and flexibility
2008-06-19 How to connect a small page NAND flash memory to STR710
This application note describes the hardware and software necessary to drive an STMicroelectronics Small Page NAND flash memory by an STR710
2001-05-01 How TMS320 tools interact with the TMS320C32's enhanced memory interface
This application note describes how to use the TMS320 floating-point DSP optimizing C compiler and assembly language tools with the variable memory width and data sizes supported by the TMS320C32's enhanced memory interface.
2004-12-13 Host communication via the asynchronous memory Interface for Blackfin processors
This app note discusses the functionality and performance of an asynchronous memory interface developed for ADSP-BF531/BF532/BF533 Blackfin processors.
2009-04-13 High-performance DDR2 SDRAM interface in Virtex-5 devices
This application note describes a 667 Mb/s DDR2 SDRAM interface implemented in a Virtex-5 device
2007-10-01 High-end memory interface needs FPGAs
As designers of high-performance systems strive to achieve higher bandwidth while meeting critical timing margins, a performance bottleneck standing in their way is the memory interface. New silicon features, along with hardware-verified reference designs, have overcome those challenges. Additionally, engineers must follow some basic rules to improve design cycle time.
2014-12-16 Getting ready for DDR memory testing
Here's a look at the first steps of DDR testing: generating DDR traffic and the criteria for a proper read/write burst pattern that will gain good test results.
2007-08-24 Free design tool implements DDR2-400 interface
Xilinx has announced support for a 400Mbps DDR2 SDRAM interface (DDR2-400) with its low-cost 90nm Spartan-3A and Spartan-3AN FPGAs
2007-12-18 FPGAs exceed 1,067Mbit/s DDR3 interface speed
Altera claims it has achieved DDR3 memory interface speeds in excess of 1,067Mbit/s with its Stratix III FPGAs.
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