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2004-07-05 Xyratex adopts Mentor Graphics PCI Express IP
Mentor Graphics Corp. has entered into an intellectual property (IP) technology relationship with Xyratex, a supplier of enterprise storage solutions targeting advanced switching (ASI) data fabrics.
2010-05-18 Wipro taps Mentor tools to reduce design time
Mentor Graphics Corp. and Wipro Technologies are partnering to continue to enable time-to-market and first-time right solutions to their global product engineering customers.
2008-07-25 What has driven Cadence to buyout Mentor
Although I have heard from a few financial analysts who think the acquisition is good for Cadence and for the industry, I continue to believe it will not work even if classical investment theory says it should.
2011-02-11 VIA adopts Mentor's Calibre PERC
VIA Technologies has adopted Mentor Graphics's Calibre PERC electrical rule checking product for enabling ESD protection on its x86 processor platforms.
2004-08-31 UMC uses Mentor Graphics FastScan ATPG tool
The FastScan, an automatic test pattern generation tool, from Mentor Graphics Corp. has been selected for UMC's 130- and 90nm digital reference flow.
2005-03-29 UMC uses Mentor embedded compression solution for production test
United Microelectronics Corp. (UMC) has adopted Mentor Graphics Corp.'s TestKompress embedded deterministic test (EDT) tool for use in 90- and 130nm reference flows.
2002-09-03 TTChip to use Mentor Graphics design tools
TTChip has licensed Mentor Graphics' ModelSim design tools for the testing and simulation of its development systems.
2008-10-09 TSMC, Mentor team on advanced physical verification
TSMC and Mentor Graphics have collaborated on physical verification solutions leveraging a new feature of the Calibre nmDRC product called "Equation-Based DRC."
2005-01-14 TSMC validates 90nm process using Mentor Graphics Calibre xRC
Mentor Graphics Corp. disclosed that Taiwan Semiconductor Corp. (TSMC) used a comparison of Calibre xRC results, field solver data and silicon measurements as part of the validation for its 90nm process technology.
2006-07-28 TSMC qualifies Mentor's Calibre nmDRC on 65nm process
Mentor Graphics announced that Taiwan Semiconductor Manufacturing Co. has qualified Calibre nmDRC for its 65nm technology.
2013-06-04 TSMC certifies Mentor EDA tools for 16nm FinFET
Mentor Graphics design and verification tools get certified for TSMC's 16nm FinFET process node. The companies also detailed their continued collaboration on 20nm physical verification kit optimisations.
2004-11-22 Toshiba adopts Mentor ADVance MS tool in LSI designs
Mentor Graphics Corp. revealed that Toshiba Corp. has adopted its analog/mixed-signal HDL language, Verilog-AMS, for the design and verification of complex analog and mixed-signal LSI (large scale integration) designs.
2007-09-20 Taiwan's MediaTek adopts Mentor's formal verification tech
Mentor Graphics announced that Taiwan's MediaTek has selected the 0-In formal verification technology to make it an integral part of its verification flow for their next generation design projects.
2006-10-17 Synopsys serves subpoena to Mentor over PTO request
Synopsys has served Mentor Graphics a subpoena demanding certain documents related to Mentor's request for reexamination of two Magma Design patents by the U.S. PTO.
2005-06-06 Startup integrates equivalence checker with Mentor's Catapult
Calypto Design Systems Inc. said that it would work with Mentor Graphics Corp. to facilitate integration between Calypto's system-level equivalence checker (SLEC) and Mentor's Catapult C synthesis tool
2007-01-26 STARC to use Mentor's analyzer tool for DFM flow
Semiconductor Technology Academic Research Center will standardize on Mentor Graphics' Calibre YieldAnalyzer for critical area analysis in their DFM flow.
2006-09-22 ST Nomadik processors feature Mentor's Nucleus Mobile OS
STMicroelectronics and Mentor Graphics Corp. collaborate to make Mentor's Nucleus Mobile OS available on STMicroelectronics' Nomadik STn880x and STn881x series of multimedia application processors.
2007-11-30 ST favors Mentor's place and route system
STMicroelectronics has taped out an advanced process, multimillion-gate STB chip using the Mentor Graphics Corp.'s Olympus-SoC place and route system.
2006-05-29 ST certifies Mentor Catapult C Synthesis Libraries
Mentor Graphics announced that STMicroelectronics has added Catapult C Synthesis libraries to its standard ASIC design kit.
2003-03-26 SMIC uses Mentor Graphics' tools in wafer production
Semiconductor Mfg Int. Corp. has chosen Mentor Graphics Corp.'s tools, including Calibre, IC Station, and Eldo, for volume production of 8-inch wafers.
2006-01-11 SMIC adopts Mentor simulation tool
Semiconductor Mfg Int. Corp. has adopted Mentor Graphics' Eldo simulation tool as an internal SPICE simulator for analog circuits.
2004-05-18 Simtek adopts Calibre xRC solution from Mentor
Simtek Corp. has adopted Mentor Graphics Corp.'s parasitic extraction solution, named Calibre xRC, for its nonvolatile memory designs.
2003-02-19 Silterra standardizes on Mentor verification tool
Silterra Malaysia Sdn. Bhd has selected Mentor Graphics Corp.'s Calibre product as its internal standard for design rule checking, layout versus schematic, and optical and process correction functionalities.
2013-06-12 SilabTech uses Mentor Graphics' tool flow for 28nm PHY
SilabTech has achieved first silicon success for their latest 28nm high-speed, mixed-signal PHY IPs using Mentor Graphics' Pyxis, Eldo, and Calibre tools.
2004-06-03 Siemens adopts Mentor Catapult C synthesis tool
Mentor Graphics Corp. announced that Siemens Information and Communications Networks has reduced C source to register transfer level (RTL) implementation time by 50 percent on a strategic project using their latest Catapult C synthesis tool.
2002-11-08 Sharp, Mentor Graphics to co-develop optimization tool
Sharp Corp. and Mentor Graphics Corp. have agreed to jointly develop a next-generation co-verification and design optimization tool that will make it possible to dramatically shorten the time required for design of large-scale, highly integrated system LSIs.
2009-04-16 SDIO software supports Mentor Nucleus RTOS
embWiSe Technologies Pvt. Ltd has announced availability of its SDIOWorx software stack on the Mentor Graphics Nucleus RTOS. embWiSe also provides an SDIO-Wi-Fi solution for Marvell 88W8686 802.11b/g chipset, integrated with the SDIOWorx
2003-01-31 RLC extraction tool supports Cadence, Mentor flows
Sequence Design has announced an RLC extraction tool that supports large mixed-signal designs in both Cadence and Mentor flows
2007-06-14 Rivals play down threat of Mentor's Sierra acquisition
Mentor Graphics' rivalsSynopsys, Cadence and Magma Designregard Mentor's Sierra acquisition as a minimal threat, and their own positions in 65/45nm IC design as strong.
2005-03-28 Renesas integrates Mentor's 0-In for assertion based verification flow
Renesas Technology Corp. has completed the integration of Mentor Graphics Corp.'s 0-In assertion synthesis technology and assertion-based verification flows with Renesas' LogicBench rapid prototyping system.
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