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2004-06-14 Mentor acquires Atair compiler technology
Mentor Graphics Corp. has acquired compiler technology and engineering resources from Atair GmbH, based in Vienna, Austria.
2006-08-10 MediaTek adopts Mentor's CDC methodology for digital media chipsets
Mentor Graphics Corp. announced that MediaTek Inc. has selected the 0-In clock-domain crossing solution for its verification methodology.
2004-10-28 Magma teams with Mentor and Logic Vision for test tools
Magma Design Automation Inc. is ensuring its Blast RTL to GDSII tool lineup works with popular test tools, as the company announced interoperability partnerships separately with Mentor Graphics and Logic Vision.
2012-10-30 KALRAY completes 256-core SoC using Mentor's sol'ns
The KALRAY MPPA-256 manycore processor is a 256-core SoC with 47MB memory using Mentor's functional verification, physical design and verification, and design-for-test flow product suites
2007-07-26 Indian design center gets $20M in tools from Mentor
Mentor Graphics is donating a complete suite of EDA tools worth over $20 million to RV-VLSI Design Center in India for use in classroom instruction and academic research.
2001-03-30 Importing a Warp post-fit netlist into Mentor Graphics' ModelSim
This application note is intended to assist Warp users in importing and simulating post-fit models into Mentor Graphics' ModelSim product.
2002-01-24 Ikos rejects Mentor's revised takeover offer
For the second time, Ikos Systems Inc.'s board of directors has recommended that Ikos' stockholders reject an unsolicited takeover bid from Mentor Graphics Corp.
2005-12-28 IBM adopts Mentor's Calibre tech
Mentor Graphics announced that IBM has adopted the patent pending Calibre encryption technology for use with IBM's 90nm, 65nm and 45nm process design kits.
2008-01-31 HKSTP, Mentor to build SoC/IC design training center
HKSTP and Mentor Graphics have agreed to jointly set up a Training Centre for SoC/IC design technology.
2006-08-25 Haier IC adopts Mentor's Eldo simulator for analog circuit design
Mentor Graphics Corp. announced that Haier IC has adopted Mentor's Eldo simulator as its standard SPICE simulator for analog circuit design.
2009-10-21 GlobalFoundries taps Mentor EDA tools
GlobalFoundries chose Mentor Graphics for its physical verification, RET, OPC and mask data preparation solutions.
2006-08-23 GiQuila adopts Mentor's hardware verification system
GiQuila has adopted Mentor Graphics' VStation hardware verification system to verify its family of graphics and multimedia ICs for handheld devices.
2006-10-26 Galileo Avionica, Mentor sign PCB design purchase agreement
Mentor Graphics announced a multi-year agreement with Galileo Avionica to standardize on Mentor's PCB Board Station RE solution for the design of complex digital boards.
2007-05-25 Fujitsu taps Mentor to improve DFM capabilities
Mentor Graphics announced that Fujitsu will use Mentor's Calibre LFD to enhance their DFM capabilities for internal product development and for external fabless customers.
2004-05-24 Fujitsu licenses Mentor 10Gb Ethernet MAC solution
Mentor Graphics Corp. has announced the licensing of its A-XGMAC 10 Gigabit Ethernet media access controller (MAC) by Fujitsu Laboratories of America Inc. (FLA).
2010-01-14 Freescale taps Mentor test, verification tech
The collaboration enables Freescale's deployment of Mentor's technologies to enhance design flows and methods
2010-05-06 Freescale fortifies partnerships with Enea, Mentor, Green Hills
Freescale has entered signed strategic alliance agreements with Enea, Green Hills Software and Mentor to establish comprehensive solutions for its QorIQ, PowerQUICC and StarCore processors
2005-03-10 Fraunhofer IIS selects Mentor Graphics Catapult C Synthesis tool
Mentor Graphics Corp. announced that the Fraunhofer Institute for Integrated Circuits IIS has selected the Mentor Graphics Catapult C Synthesis tool for use in next-generation digital broadcast applications
2006-01-12 Faraday adopts Mentor's Eldo simulation tool
Mentor Graphics and Faraday Technology jointly announced that Faraday has adopted Mentor's Eldo simulation tool as their internal SPICE simulator for cell library and IP characterization.
2003-07-24 Faraday adopts Mentor solution for parasitic extraction
Faraday Technology has selected Mentor Graphics' Calibre xRC product as its transistor level and GDSII-based gate-level parasitic extraction tool for SoCs.
2011-01-12 EVE readies defense against Mentor’s infringement suits
EVE is preparing to defend itself against Mentor’s patent infringement suits, rallying the EDA community to bring Mentor back to reason
2006-12-20 eInfochips verification component supports Mentor's Questa
A component that provides building blocks for efficient design-under-test in module and system-level verification for Mentor Graphics' Questa Vanguard program, including assertion testing, is now available from eInfochips Inc.
2005-11-04 Diagnostic tool from Mentor enhances semiconductor yield
Mentor Graphics Corp.'s YieldAssist diagnostic tool to enhance semiconductor yield and expand the DFT product portfolio and platform.
2008-08-26 Despite Q2 loss, Mentor remains positive
Mentor Graphics Corp. made a loss of $17.2 million on revenue of $182.4 million in Q2 ended July 31.
2013-11-13 CSR, Mentor Graphics team up to cut OEM dev't time
The partnership aims to deliver a robust, automotive grade connected platform for developing in-vehicle infotainment (IVI) solutions.
2008-10-14 Comment: Mentor adopts a better strategy
I have been very excited by Mentor Graphics Corp.'s acquisition of Flomerics because it represents the first time that a traditional EDA vendor has recognized and acted upon a system that is more than simply the electronic components.
2008-06-20 Cadence-Mentor merger a 'bad idea', analyst says
A veteran EDA analyst said Cadence Design Systems is under pressure and may lose its top spot in the electronic design automation sector, and its proposed $1.6 billion merger with Mentor Graphics is a 'bad idea.'
2007-10-16 Cadence, Mentor unify SystemVerilog method
Cadence Design Systems Inc. and Mentor Graphics Corp. have joined forces to promote a common approach to the verification of design files based on SystemVerilog.
2007-08-22 Cadence, Mentor team on SystemVerilog methodology
Cadence Design Systems Inc. and Mentor Graphics Corp. have partnered to standardize on a verification methodology based on the IEEE Std. 1800-2005 SystemVerilog standard.
2006-09-01 Cadence, Mentor spar in high-speed realm
The EDA rivals find themselves at odds as the quest for a single simulation approach suitable for high-speed designs continues.
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