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2011-12-20 Metallization firing system touts 200C/s ramp rate
The three-belt, three-speed machine boasts more than 99.99 percent yield that claims to exceed industry standard for metallization firing.
2001-04-01 Back-end copper metallization for flip chip
The IC industry's move toward the broad implementation of copper for back-end metallization is being driven by cost reduction that results from the use of an electroplating process.
2002-05-14 Novellus opens manufacturing facility in Oregon
Novellus Systems Inc. has opened a manufacturing facility in Tualatin, Oregon, in a bid to expand its engineering and manufacturing infrastructure.
2002-01-23 Axon, Micron ink license agreement for PMC technology
Axon Technologies Corp. and Micron Technology Inc. have entered into a non-exclusive commercial license agreement for Axon's patented programmable metallization cell (PMC) technology.
2002-05-13 An electrostatically actuated micro-relay
This application note illustrates the design, function and purpose of the electrostatically actuated microrelay.
2008-06-13 Alchimer picks Lenix as Korea representative for TSV
Alchimer, a provider of nanometric films for through-silicon via (TSV) metallization, has appointed Lenix as its representative in Korea.
2012-03-26 130nm CMOS logic backend tech unleashed
SilTerra Malaysia released the CL130AL that offers single poly up to six layers of aluminum metallization, borderless contacts and via with USG inter-metal dielectric.
2008-09-16 Valuing substrate parasitics in RFIC designs
Often, there is a need to simulate RFIC designs with substrate parasitics to accurately represent high-frequency effects in actual silicon. Generally, parasitics appear from a chip's surface layers, especially from metallization routing and coupling, or from the RC parasitics of the silicon substrate.
2010-09-09 Silicon solar cells show 19.4% conversion
Copper-based front-side metallization makes the cells cheaper for future industrial production.
2001-01-01 Contract manufacturing and flip-chip interconnect design
This technical article describes present contract manufacturers' dilemma over the entire flip-chip manufacturing process. It also describes the use of a planarizing surface which provides a uniform surface to fabricate solder interconnect structures and redistribution metallization.
2007-11-22 Applied to acquire PV cell test system provider
Applied Materials announced it will acquire Italy-based supplier of automated metallization and test systems for manufacturing crystalline silicon (c-Si) PV cells Baccini S.p.A for $330 million in cash.
2008-02-05 Applied beefs up solar cell biz with Baccini buyout
Applied Materials has acquired Baccini S.p.A., Italy-based supplier of automated metallization and test systems for manufacturing crystalline silicon photovoltaic cells, for $334 million in cash.
2008-09-05 X-Fab Sarawak all set to start 0.35?m process tech
X-Fab Silicon Foundries' Malaysian facility in Kuching, Sarawak, with its 200mm production line, now is fully qualified for volume production and second sourcing of the company's 0.35?m high-voltage process technology called XH035.
2008-08-13 World's first 3D chip technology surfaces
The world's first 3D chip process is ready for licensing from the fabless semiconductor design house BeSang.
2008-06-06 Will 3D through-silicon vias break into mainstream?
The 3D technology based on through-silicon vias technology took center stage at the IEEE 2008 International Interconnect Technology Conference but there is still no consensus just how the industry will bring the long-awaited technology into the mainstream.
2010-04-16 When will memristors be ready for prime time?
While memristors represent a potential revolution in electronic-circuit theory akin to the invention of the transistor, it will take a killer application to get it off the ground.
2011-11-22 Wafer packaging fab opens in Taiwan
STATS ChipPAC has increased production capacity with the completion of its 300mm wafer bump and WLCSP facility.
2003-01-15 Vishay HDIs feature enhanced signal routing
Vishay Intertechnology Inc. has announced the release of thin-film, high-density interconnects with enhanced signal routing.
2006-07-07 ViASIC announces 2-mask standard-metal Structured ASIC fabric
To address the requirements of the reconfigurable SoC market, ViASIC have introduced a new Structured ASIC fabric called DuoMask.
2011-02-04 Used gear supplier launches R&D foundry service
Aimed at discrete manufacturers, foundries, universities and fabless design houses, the new service covers fab and testing capabilities, PVD deposition capability, metrology and processing of various metals.
2009-04-09 Unlock Micron's 50nm DRAM technology
With their latest 50nm process technology, Micron Technology Inc. seems to have struck the right balance between investment in new technologies and conservative design decisions.
2009-01-19 Ultrathin wafer bonding system installed in Taiwan lab
EV Group (EVG) has installed an EVG 500 series wafer-bonding system at Brewer Science Inc.'s Taiwan applications lab.
2004-10-19 TSMC, Freescale to develop 65nm SOI technology
Taiwan Semiconductor Mfg Co. (TSMC) and Freescale Semiconductor Inc. have signed an agreement to jointly develop a next-generation silicon-on-insulator (SOI) transistor front-end technology targeted for the 65nm advanced CMOS process node.
2011-08-08 Tower moves SBL13 process to Israel
Specialty foundry Tower has decided to move its SBL13 process to Israel, giving way to development of their SiGe technology and sourcing capability for customers.
2006-05-17 TI signs up Chartered for 65nm production
Texas Instruments is tweaking its manufacturing strategy, adding Chartered Semiconductor Mfg as a third foundry for 65nm production.
2007-04-02 TI Fellow details digital micromirror apps
Larry Hornbeck, Emmy winner for his invention of the digital micromirror device, told EE Times that TI has still more applications up its sleeve for the digital micromirror.
2002-08-08 Thin-film chip attenuators feature various termination styles
State of the Art Inc. has enhanced and expanded its line of thin-film chip attenuators.
2016-03-15 The endless pursuit of smaller packages
In this article, we explore the creativity in semiconductor package integration, while anticipating the release of the Samsung's Galaxy S7 and the iPhone 7.
2012-07-26 Techniques, procedures for die bonding
Here's a look at various techniques for die bonding, a process of connecting die to the package for communication to the outside world.
2011-02-11 Technique promises nanoscale resolution with visible light
The new technique uses multiphoton absorption with photoresists to achieve nanoscale resolution with focused visible light, thus delaying or even eliminating the need to move to extreme UV light sources.
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