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2002-12-06 Metastability in MACH Devices
This application describes metastability in MACH devices, which occurs in digital systems where inputs are not synchronized to their own internal clocks.
2000-06-28 Metastability Considerations
This application note provides designers with formulas and test measurements to calculate the probability of failure metastability considerations. Design techniques for minimizing metastability are also provided.
2008-10-06 Metastability characterization report for Actel flash FPGAs
This document discusses a description of metastability equations followed by metastability characterization of ProASIC, ProASICPLUS, ProASIC3, and ProASIC3E FPGAs
2000-12-06 Metastability and the ECLinPS family
This application note examines the concept of metastability and provides a theoretical discussion of how it occurs, including examples of the metastable condition.
2005-06-20 Metastability and the ECLinPS family
This app note examines the concept of metastability and provides a theoretical discussion of how it occurs, including examples of the metastable condition
2001-04-23 Metastability
This application note describes metastability in flip-flops and suggests some methods to reduce the problem of metastability in these digital circuits.
2013-12-02 Grasping metastability (Part 1)
Find out how metastability can be triggered in registers.
2004-05-18 0-In tool verifies metastability effects
Claiming a "breakthrough" solution for the automatic verification of metastability effects, 0-In Design Automation is preparing Archer CDC-FX, an addition to its clock-domain crossing (CDC) verification tool.
2004-11-16 Taking GALS to 65nm designs
Emerging globally asynchronous, locally synchronous SoC design architectures offer a powerful way to solve interconnect issues in these superintegrated chips.
2012-12-07 Synchroniser with programmable MTBF capabilities
Here's a high frequency synchroniser circuit with programmable mean-time-between-failure capabilities well suited for high frequency clock gating and input signal synchronisation applications.
2013-10-22 Structural, reset faults in SoC designs (Part 2)
Know some of the basic structural issues in reset architectures used in advanced nanometre scale SoC designs.
2013-10-16 Structural, reset faults in SoC designs (Part 1)
Here's a two-part survey of some of the basic structural issues in reset architectures used in advanced nanometre scale SoC designs.
2012-02-29 Designing high frequency synchronizer with programmable MTBF features
Read about a high frequency synchronizer circuit with programmable mean-time-between-failure capabilities that is well suited for high frequency clock gating and input signal synchronization applications.
2001-03-27 Are your PLDs metastable?
This application note provides a detailed description of the metastable behavior in PLDs from both circuit and statistical viewpoints.
2015-02-12 Verilog-AMS vs SPICE view for power management
Verilog-AMS is a behavioural abstraction of the circuit that sacrifices accuracy for the sake of run time, while SPICE does exactly the opposite. Here's a comparative analysis from a power management perspective.
2008-02-18 Use segmented memory to improve DAQ
Given the high sample rates and bandwidths of today�s oscilloscopes, the critical issue is optimizing the quality of information captured by the instrument. This includes how to capture multiple events at a sufficiently high horizontal resolution for effective analysis and how to optimize the use of memory by storing and displaying only the necessary data.
2003-08-12 Silicon Metrics wins key patent
Silicon Metrics Corp. has won a U.S. patent on some of the core technology used in its EDA characterization and modeling software.
2011-08-22 How to reset an FPGA
Know the various reset options available for FPGAs, as well as their advantages and disadvantages.
2012-08-08 Grasping power awareness in RTL design analysis
Find out how formats such as CPF and UPF play a key role in capturing power intent for RTL design analysis and verification.
2014-05-23 Enable accelerated SoC physical design at RTL
In this article, we provide a review of the essential points to consider in order to ensure a smooth transition between the logical and physical worlds.
2011-02-03 DesignCon presents ways to cut design time
Among the methods proposed to speed up design schedules are the formation of small integrated design teams and the reengineering of design tools with parallel processing.
2009-03-17 Design Guidelines and Timing Closure Techniques for HardCopy ASICs
This application note covers topics from a timing closure perspective, for the successful migration to HardCopy ASICs from Altera's FPGAs
2015-05-14 Connecting passive components to logic gates
By adding a few passive components, you can make circuits such as level converters, frequency multipliers, phase detectors, line drivers, and pulse changers.
2013-10-02 Blue Pearl Software Suite v.7.1 boasts CDC enhancements
Release 7.1 new features include the User Grey Cell, CDC Waivers, CDC checks more granular, Black box signal direction detection and FPGA-vendor specific options pages.
2014-03-04 Analyse CDC violations in million-gate SoC (Part 1)
Learn how to constrain the design to avoid unwanted violations and analyse the remaining CDC paths flagged by tool.
2002-07-09 Actel FPGA family delivers >500MHz operation
Actel Corp. has launched its Axcelerator family of FPGAs that range from 125,000 to 2 million system gates, delivering >500MHz operation and up to 100 percent resource utilization.
2012-10-02 'Puffin' gives intrinsic security for gamers,phones
The 'Puffin' project has already found that software can detect the die-specific differences in graphics processors.
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