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2009-11-10 Samsung slims down multi-die memory package
Samsung claims the thinnest multi-die memory package measuring 0.6mm in height, just half the thickness of a conventional memory package of eight stacked chips or dies.
2005-05-17 Philips Semiconductor CTO outlines system-in-package challenges
The next step forward in integration has to address system-in-package (SIP) issues and needs EDA tools with broader scope and greater standardization of approach, according to Rene Penning de Vries, chief technology officer of Philips Semiconductors
2008-08-27 Cadence tool steps up IC package, SiP designs
The release of SPB 16.2, due in November of this year, from Cadence Design Systems, delivers advanced IC package/system-in-package miniaturization, design cycle reduction and DFM-driven design, along with a new power integrity modeling solution
2003-03-28 ASAT qualifies new leadless plastic package
ASAT Holdings Ltd has announced the qualification and addition of the TAPP technology to its portfolio of leadless packages.
2005-10-14 Multi-die packaging gains ground, says analyst
Applications such as cellular telephones, Bluetooth, and digital cameras are going to cause the market for high-density packaging market to grow by 32 percent in 2005 to 1.5 billion units, according The Information Network, a market research company.
2002-01-18 UTAC teams up with M-Systems on MCPs
United Test and Assembly Center Ltd (UTAC) is collaborating with M-Systems to deliver MCP (Multi-Chip Package) leaded and array packages
2013-11-22 Novel dielectric material to enhance eWLB packages
Nanium released an improved dielectric material and process solution for its fan-out wafer-level packaging (FOWLP) technology, embedded wafer-level ball grid array (eWLB).
2015-03-09 IoT drives chip packaging innovation
The need for high performance multi-functional devices in a single package is pushing the industry to innovate in multi-chip packaging. This high level of integration has presented huge challenge
2014-10-02 Optimise power designs with IGBT thermal calculations
Evaluating the temperature of the semiconductor dice in a multi-die package requires additional analytical techniques compared to those applicable for single die. This article shows how to do it properly.
2012-10-11 TSMC releases 20nm, CoWoS design reference
The silicon-validated CoWoS Reference Flow enables multi-die integration to support high bandwidth, low power and can achieve fast time-to-market for 3D IC designs
2014-05-14 Intel sets sights on a foundry goal for innovation
The chip giant has been raising the profile of its foundry business over the last year, mainly in pursuit of growth and profit. It has also expanded its deal with Altera to produce multi-die devices
2014-04-25 TSMC fleshes out IC line-up with shrunk TSVs
Based on its work on chip stacks, TSMC will launch in July an enhanced version of the 16nm FinFET technology with up to 18 per cent faster data rates and lower leakage, in addition to a planned 10mm and 7mm processes.
2003-04-28 Epson licenses Tessera packaging technology
Seiko Epson Corp. has entered a technology license agreement with Tessera Inc. to utilize the latter's semiconductor packaging technology in ASICs and specialty memory products.
2014-09-01 White-chip scale packages offer up to 80% cost reduction
Rated for input power up to 3W, the the ReadyMount Enhanced CSP from SemiLEDs is a fully packaged white emitter SMD component, ready for surface mounting on any board level module or COB application.
2012-10-17 TSMC names EDA partners for CoWoS, 20nm
TSMC has validated technologies from Cadence, Mentor and ANSYS for use in its 20nm and CoWoS design infrastructure.
2003-05-08 Stratos rolls stackable SFF transceivers
Stratos Lightwave has announced the availability of what it claims to be the industry's first stackable SFF transceivers for GbE and Fibre Channel apps.
2002-05-20 Stratos RJ Format optical transceivers meet Infiniband specs
Stratos Lightwave Inc. has announced the shipment of its RJ Format of optical transceivers that comply with the Infiniband standard, and are intended for use in heavy-traffic environments.
2015-07-21 Semicon West highlights 10 chip trends
During the recent Semicon West, executives from a number of chip companies discussed the ongoing developments on semiconductors technology.
2010-09-15 RCP technology manufactured in 300mm format
Nepes to manufacture Freescale technology that replaces deployed ball grid array packaging
2015-06-29 OSATS: Wafer-level packaging limitations hard to dismiss
The recent SEMI Packaging Tech Seminar focused on the need, in terms of under yield and packaging cost pressures, to move from fan-out wafer-level-packaging to fan-out panel-level-packaging.
2014-09-12 Intel plans to extend Moore's Law to 7nm
Chipmakers generally don't expect the much-delayed extreme ultraviolet lithography in time for 10nm chips, but many still hold out hopes it could be ready for a 7nm generation.
2014-06-24 FPGAs afford server boosts in datacentres
Bing is rolling out Stratix-based fabric on servers to accelerate processing of customer searches, an approach that Microsoft revealed to improve ranking server throughput by 95 per cent.
2014-07-01 Chip industry to face hurdles brought by 20nm tech
Executives from two capital equipment firms said chip vendors face the challenges brought by higher costs and complexities due to tighter margins, new processes and materials at 20nm and beyond.
2009-10-27 Assembly guidelines for MicroFET-6 packaging
This application note focuses on the soldering and back end processing of the MicroFET-6.
2009-10-26 Assembly guidelines for Dual Power56 Packaging
This application note focuses on the soldering and back end processing of the Dual Power56.
2015-06-10 Altera touts next-gen high-end programmable logic devices
The Stratix 10 FPGAs and SoCs leverage Altera's HyperFlex FPGA fabric architecture built on the Intel 14nm Tri-Gate process to provide 2X higher core performance over previous generation FPGAs.
2014-07-31 3D-IC: Taking the next steps towards broad adoption
Technology firms are applying manufacturing intelligence across test operations to bring the associated costs in line with required levels of profitability.
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