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2016-04-01 Marvell to use SerDes technology for multi-die products
The Glasswing chip-to-chip technology from Swiss startup, Kandou, is based on the Chord signaling method, which produces an energy efficiency that enables architectural innovation.
2014-05-14 Intel sets sights on a foundry goal for innovation
The chip giant has been raising the profile of its foundry business over the last year, mainly in pursuit of growth and profit. It has also expanded its deal with Altera to produce multi-die devices
2003-04-28 Epson licenses Tessera packaging technology
Seiko Epson Corp. has entered a technology license agreement with Tessera Inc. to utilize the latter's semiconductor packaging technology in ASICs and specialty memory products
2014-09-01 White-chip scale packages offer up to 80% cost reduction
Rated for input power up to 3W, the the ReadyMount Enhanced CSP from SemiLEDs is a fully packaged white emitter SMD component, ready for surface mounting on any board level module or COB application.
2012-10-17 TSMC names EDA partners for CoWoS, 20nm
TSMC has validated technologies from Cadence, Mentor and ANSYS for use in its 20nm and CoWoS design infrastructure.
2014-04-25 TSMC fleshes out IC line-up with shrunk TSVs
Based on its work on chip stacks, TSMC will launch in July an enhanced version of the 16nm FinFET technology with up to 18 per cent faster data rates and lower leakage, in addition to a planned 10mm and 7mm processes.
2010-11-10 Quickpath IP gets into Achronix FPGAs
Intel's Quickpath IP core for processor communications will be integrated into FPGAs from Achronix that will be manufactured by Intel.
2015-06-29 OSATS: Wafer-level packaging limitations hard to dismiss
The recent SEMI Packaging Tech Seminar focused on the need, in terms of under yield and packaging cost pressures, to move from fan-out wafer-level-packaging to fan-out panel-level-packaging.
2013-11-22 Novel dielectric material to enhance eWLB packages
Nanium released an improved dielectric material and process solution for its fan-out wafer-level packaging (FOWLP) technology, embedded wafer-level ball grid array (eWLB).
2015-03-09 IoT drives chip packaging innovation
The need for high performance multi-functional devices in a single package is pushing the industry to innovate in multi-chip packaging. This high level of integration has presented huge challenge.
2014-09-12 Intel plans to extend Moore's Law to 7nm
Chipmakers generally don't expect the much-delayed extreme ultraviolet lithography in time for 10nm chips, but many still hold out hopes it could be ready for a 7nm generation.
2014-07-01 Chip industry to face hurdles brought by 20nm tech
Executives from two capital equipment firms said chip vendors face the challenges brought by higher costs and complexities due to tighter margins, new processes and materials at 20nm and beyond.
2009-10-27 Assembly guidelines for MicroFET-6 packaging
This application note focuses on the soldering and back end processing of the MicroFET-6.
2009-10-26 Assembly guidelines for Dual Power56 Packaging
This application note focuses on the soldering and back end processing of the Dual Power56.
2003-03-28 ASAT qualifies new leadless plastic package
ASAT Holdings Ltd has announced the qualification and addition of the TAPP technology to its portfolio of leadless packages.
2009-10-23 34nm MLC NAND touts improved data transfer rates
Micron offers a 34nm MLC enterprise NAND device that provides a cost-effective way to reliably double their flash-based enterprise storage capacity.
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