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2006-12-08 SystemC transaction-level standard released for review
Taking a step towards the interoperability of SystemC transaction-level models, the Open SystemC Initiative has released a draft SystemC Transaction-Level Modeling 2.0 kit for public review.
2005-01-20 SystemC synthesis under $2,000 debuts
Orange Tree Technologies and SystemCrafter have teamed to make SystemC synthesis more affordable for the masses
2003-02-28 SystemC seen accelerating simulation
SystemC is seeing increasing use as a way of accelerating simulation, according to speakers at the DVCon Design and Verification Conference
2001-04-01 SystemC revision drives toward synchronized system-level design
Synopsys and CoWare launches the SystemC to create a standardized dialect of C/C++ for both hardware and software design. SystemC provides a C/C++ class library that represents hardware concepts such as concurrency for designers to utilize
2003-03-03 Summit tool beefs up SystemC
Summit Design Inc. launched its Visual Elite 3.1 which included FastC to better reach out to HDL designers.
2006-07-13 Summit Design launches IP interoperability initiative
Summit Design announced the launch of its Intellectual Property Initiative, which aims to address IP interoperability issues at the system level
2001-05-16 Questions for SystemC
OSCI is supposed to be an "open" and independent standards effort, but Synopsys still has total control over the license agreement
2003-09-11 OSCI group seeks IEEE nod for SystemC
The Open SystemC Initiative is looking to cement the language's legitimacy by submitting it to the IEEE for standards approval.
2003-09-02 New OSCI board strives for SystemC approval
The Open SystemC Initiative (OSCI) wants to cement itself as a viable language for large silicon platforms and SoCs.
2004-04-20 Mentor links SystemC to emulation
Mentor Graphics has announced a "transaction based" interface between SystemC testbenches and its VStation emulators
2005-09-01 Engineers write up SystemC TLM concepts
Engineers at STMicroelectronics claim that SystemC transaction-level modeling will be the next SoC design methodology
2003-05-07 CoWare to unveil native SystemC tool
The company will release what it calls the first system-level verification tool built specifically for SystemC
2003-11-24 ARM rolls out transaction-level SystemC models
ARM Ltd has announced the availability of the transaction-level SystemC models of its cores that are targeted for system-level verification
2007-01-26 Synopsys contributes virtual platform tech to OSCI
EDA software provider Synopsys Inc. has contributed a key technology for the development of Virtual Platforms based on SystemC to industry group Open SystemC Initiative (OSCI).
2005-06-15 STMicro bares major breakthrough in SoC design
STMicroelectronics has revealed the publication of a book on chip design methodology.
2008-03-10 More groups push standards for virtual prototyping
New players are expected to push forward efforts to create standards for virtual prototyping as the next wave in system and software development, to allow tools and simulation models from various suppliers work together.
2013-07-31 ST, ARM and Cadence team up for tool, model interoperability
The collaboration of ST, ARM and Cadence aims to increase model and tool interoperability for electronic system-level (ESL) design at the transaction-level.
2006-03-31 Aldec offers 90-day free access to Riviera Verilog simulator
Aldec announced full simulation support in Riviera for the open-source UltraSPARC T1 from Sun Microsystems
2009-01-22 Tools support layered modeling based on TLM-2.0
Mentor Graphics Corp. has announced a scalable design methodology based on transaction-level modeling (TLM) that allows a single model to be taken from design concept to implementation.
2001-05-16 Syntax raises RTL abstraction level
A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages.
2008-02-26 Rhines on EDA: End 'endless verification'
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification.
2008-09-30 Intel, Chartered criticize chip IP industry
The semiconductor intellectual property (IP) industry has been the virtual and ongoing punching bag in the IC business.
2011-06-23 Accellera, OSCI team up unifies EDA standards
Accellera and OSCI are joining forces to create a single organization, a move that will accelerate development of system-level standards as well as chip design and verification standards.
2002-06-12 Standards inch forward with skeptics in tow
Two standards efforts will take major steps forward at the 39th Design Automation Conference, as the OpenAccess Coalition announces four additional EDA vendor members and much of the EDA community lines up behind Accellera's new SystemVerilog standard.
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